URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Diff between revs 87 and 90

Rev 87	Rev 90
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.3 2003/01/21 13:51:30 simont`
	`// add include oc8051_defines.v`
	`//`
`// Revision 1.2 2003/01/13 14:14:41 simont`	`// Revision 1.2 2003/01/13 14:14:41 simont`
`// replace some modules`	`// replace some modules`
`//`	`//`
`// Revision 1.1 2002/11/05 17:22:27 simont`	`// Revision 1.1 2002/11/05 17:22:27 simont`
`// initial import`	`// initial import`
Line 216...	Line 219...
`.t1_ow(tf1));`	`.t1_ow(tf1));`

`//`	`//`
`// interrupt control`	`// interrupt control`
`// IP, IE, TCON`	`// IP, IE, TCON`
`oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),`	`oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),`
`.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),`	`.ack(int_ack), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),`
`.wr(we), .wr_bit(wr_bit_r),`	`.wr(we), .wr_bit(wr_bit_r),`
`.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),`	`.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),`
`.ie0(int0), .ie1(int1),`	`.ie0(int0), .ie1(int1),`
`.uart_int(uart_int),`	`.uart_int(uart_int),`