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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc2.v] - Diff between revs 112 and 116

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Rev 112	Rev 116
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2003/04/04 10:34:13 simont`
	`// change timers to meet timing specifications (add divider with 12)`
	`//`
`// Revision 1.1 2003/01/13 14:13:12 simont`	`// Revision 1.1 2003/01/13 14:13:12 simont`
`// initial import`	`// initial import`
`//`	`//`
`//`	`//`
`//`	`//`
Line 57...	Line 60...
`//synopsys translate_on`	`//synopsys translate_on`



`module oc8051_tc2 (clk, rst,`	`module oc8051_tc2 (clk, rst,`
`wr_addr, rd_addr,`	`wr_addr,`
`data_in, data_out, bit_out,`	`data_in, bit_in,`
`wr, wr_bit, bit_in,`	`wr, wr_bit,`
`t2, t2ex,`	`t2, t2ex,`
`rclk, tclk,`	`rclk, tclk,`
`brate2, tc2_int,`	`brate2, tc2_int,`
`pres_ow);`	`pres_ow,`
	`//registers`
	`t2con, tl2, th2, rcap2l, rcap2h);`

`input [7:0] wr_addr,`	`input [7:0] wr_addr,`
`data_in,`	`data_in;`
`rd_addr;`
`input clk,`	`input clk,`
`rst,`	`rst,`
`wr,`	`wr,`
`wr_bit,`	`wr_bit,`
`t2,`	`t2,`
`t2ex,`	`t2ex,`
`bit_in,`	`bit_in,`
`pres_ow; //prescalre owerflov`	`pres_ow; //prescalre owerflov`
`output [7:0] data_out;`	`output [7:0] t2con,`
	`tl2,`
	`th2,`
	`rcap2l,`
	`rcap2h;`
`output tc2_int,`	`output tc2_int,`
`bit_out,`
`rclk,`	`rclk,`
`tclk,`	`tclk,`
`brate2;`	`brate2;`

`reg [7:0] data_out;`

`reg brate2;`	`reg brate2;`
`reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;`	`reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;`

`reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;`	`reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;`
Line 106...	Line 112...
`assign exen2 = t2con[3];`	`assign exen2 = t2con[3];`
`assign tr2 = t2con[2];`	`assign tr2 = t2con[2];`
`assign ct2 = t2con[1];`	`assign ct2 = t2con[1];`
`assign cprl2 = t2con[0];`	`assign cprl2 = t2con[0];`

`assign bit_out = t2con[rd_addr[2:0]];`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`begin`	`begin`
`if (rst) begin`	`if (rst) begin`
t2con <= #1 `OC8051_RST_T2CON;	t2con <= #1 `OC8051_RST_T2CON;
end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin	end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
Line 237...	Line 241...
`t2_r <= #1 1'b0;`	`t2_r <= #1 1'b0;`
`end else if (t2) begin`	`end else if (t2) begin`
`tc2_event <= #1 1'b0;`	`tc2_event <= #1 1'b0;`
`t2_r <= #1 1'b1;`	`t2_r <= #1 1'b1;`
`end else if (!t2 & t2_r) begin`	`end else if (!t2 & t2_r) begin`
`// end if (t2_r) begin`
`tc2_event <= #1 1'b1;`	`tc2_event <= #1 1'b1;`
`t2_r <= #1 1'b0;`	`t2_r <= #1 1'b0;`
`end else begin`	`end else begin`
`tc2_event <= #1 1'b0;`	`tc2_event <= #1 1'b0;`
`end`	`end`
`end`	`end`

`always @(rd_addr or t2con or tl2 or th2 or rcap2l or rcap2h)`
`begin`
`case (rd_addr)`
`OC8051_SFR_RCAP2H: data_out = rcap2h;
`OC8051_SFR_RCAP2L: data_out = rcap2l;
`OC8051_SFR_TH2: data_out = th2;
`OC8051_SFR_TL2: data_out = tl2;
`default: data_out = t2con;`
`endcase`

`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc2.v] - Diff between revs 112 and 116