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https://opencores.org/ocsvn/8051/8051/trunk
[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Diff between revs 148 and 172
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| Rev 148 |
Rev 172 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.30 2003/06/03 16:51:24 simont
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// include "8051_defines" added.
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//
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// Revision 1.29 2003/05/07 12:36:03 simont
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// Revision 1.29 2003/05/07 12:36:03 simont
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// chsnge comp.des to des1
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// chsnge comp.des to des1
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//
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//
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// Revision 1.28 2003/05/06 09:41:35 simont
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// Revision 1.28 2003/05/06 09:41:35 simont
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
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| Line 162... |
Line 165... |
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`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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t2_i, t2ex_i,
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t2_i, t2ex_i,
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`endif
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`endif
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// BIST
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`ifdef OC8051_BIST
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scanb_rst,
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scanb_clk,
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scanb_si,
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scanb_so,
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scanb_en,
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`endif
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// external access (active low)
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// external access (active low)
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ea_in
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ea_in
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);
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);
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Line 247... |
`ifdef OC8051_TC2
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`ifdef OC8051_TC2
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input t2_i, // counter 2 input
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input t2_i, // counter 2 input
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t2ex_i; //
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t2ex_i; //
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`endif
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`endif
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`ifdef OC8051_BIST
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input scanb_rst;
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input scanb_clk;
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input scanb_si;
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output scanb_so;
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input scanb_en;
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`endif
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wire [7:0] dptr_hi,
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wire [7:0] dptr_hi,
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dptr_lo,
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dptr_lo,
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ri,
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ri,
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data_out,
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data_out,
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op1,
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op1,
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| Line 396... |
Line 415... |
.wr_addr(wr_addr),
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.wr_addr(wr_addr),
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.bit_addr(bit_addr_o),
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.bit_addr(bit_addr_o),
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.wr_data(wr_dat),
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.wr_data(wr_dat),
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.wr(wr_o && (!wr_addr[7] || wr_ind)),
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.wr(wr_o && (!wr_addr[7] || wr_ind)),
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.bit_data_in(desCy),
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.bit_data_in(desCy),
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.bit_data_out(bit_data));
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.bit_data_out(bit_data)
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`ifdef OC8051_BIST
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,
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.scanb_rst(scanb_rst),
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.scanb_clk(scanb_clk),
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.scanb_si(scanb_si),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en)
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`endif
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);
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//
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//
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oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
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oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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