| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.17 2002/11/05 17:23:54 simont
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// add module oc8051_sfr, 256 bytes internal ram
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//
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// Revision 1.16 2002/10/28 14:55:00 simont
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// Revision 1.16 2002/10/28 14:55:00 simont
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// fix bug in interface to external data ram
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// fix bug in interface to external data ram
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//
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//
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// Revision 1.15 2002/10/23 16:53:39 simont
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// Revision 1.15 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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// fix bugs in instruction interface
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| Line 61... |
Line 64... |
// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_top (rst, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, dat_i,
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module oc8051_top (rst_i, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, ddat_i,
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icyc_o, dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
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icyc_o, ddat_o, dadr_o, dwe_o, dack_i, dstb_o, dcyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
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p1_out, p2_out, p3_out, rxd, txd, t0, t1);
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p1_out, p2_out, p3_out, rxd, txd, t0, t1, t2, t2ex);
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//
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//
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// rst (in) reset - pin
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// rst_i (in) reset - pin
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// clk (in) clock - pin
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// clk (in) clock - pin
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// iadr_o (out) program rom addres (pin + internal)
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// iadr_o (out) program rom addres (pin + internal)
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// int0 (in) external interrupt 0
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// int0 (in) external interrupt 0
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// int1 (in) external interrupt 1
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// int1 (in) external interrupt 1
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// dat_i (in) exteranal ram input
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// dat_i (in) exteranal ram input
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// dat_o (out) exteranal ram output
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// dat_o (out) exteranal ram output
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// adr_o (out) external address
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// adr_o (out) external address
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// we_o (out) write to external ram
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// dwe_o (out) write to external ram
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// stb_o
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// dstb_o
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// ack_i
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// ack_i
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// idat_i (in) data from external program rom
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// idat_i (in) data from external program rom
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// istb_o (out) strobe to program rom
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// istb_o (out) strobe to program rom
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// iack_i (in) acknowlage from external rom
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// iack_i (in) acknowlage from external rom
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// icyc_o (out)
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// icyc_o (out)
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| Line 90... |
Line 93... |
//
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//
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//
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//
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input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i, iack_i;
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input rst_i, clk, int0, int1, ea, rxd, t0, t1, dack_i, iack_i, t2, t2ex;
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input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in;
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input [7:0] ddat_i, p0_in, p1_in, p2_in, p3_in;
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input [31:0] idat_i;
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input [31:0] idat_i;
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|
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output we_o, txd, stb_o, cyc_o, istb_o, icyc_o;
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output dwe_o, txd, dstb_o, dcyc_o, istb_o, icyc_o;
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output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
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output [7:0] ddat_o, p0_out, p1_out, p2_out, p3_out;
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//output [15:0] rom_addr, ext_addr;
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output [15:0] adr_o, iadr_o;
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output [15:0] dadr_o, iadr_o;
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out, sp;
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
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wire [7:0] op1, op2, op3;
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wire [7:0] op1, op2, op3;
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wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
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wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
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wire [7:0] sp, sp_w;
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wire [15:0] pc;
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wire [15:0] pc;
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//
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wire rst;
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// data output is always from accumulator
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assign rst = rst_i;
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assign dat_o = acc;
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assign cyc_o = stb_o;
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assign dcyc_o = dstb_o;
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assign icyc_o = istb_o;
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assign icyc_o = istb_o;
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assign op1 = idat_i[31:24];
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assign op2 = idat_i[23:16];
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assign op3 = idat_i[15:8];
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//
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//
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// ram_rd_sel ram read (internal)
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// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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// ram_wr_sel ram write (internal)
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// src_sel1, src_sel2 from decoder to register
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// src_sel1, src_sel2 from decoder to register
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// imm_sel immediate select
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wire src_sel3;
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wire [1:0] ram_rd_sel, src_sel1, src_sel2;
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wire [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
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wire [2:0] ram_wr_sel, imm_sel;
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wire [2:0] src_sel2, src_sel1;
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//
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//
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// wr_addr ram write addres
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// wr_addr ram write addres
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// ram_out data from ram
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// ram_out data from ram
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// sp stack pointer output
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// rd_addr data ram read addres
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// rd_addr data ram read addres
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// rd_addr_r data ram read addres registerd
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// rd_addr_r data ram read addres registerd
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wire [7:0] wr_addr, ram_data, ram_out, rd_addr, rd_addr_r, sfr_out;
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wire [7:0] ram_data, ram_out, sfr_out, wr_dat;
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wire [7:0] wr_addr, rd_addr;
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wire sfr_bit;
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wire sfr_bit;
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//
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//
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// src_sel1_r, src_sel2_r src select, registred
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// cy_sel carry select; from decoder to cy_selct1
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// cy_sel carry select; from decoder to cy_selct1
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// rom_addr_sel rom addres select; alu or pc
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// rom_addr_sel rom addres select; alu or pc
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// ext_adddr_sel external addres select; data pointer or Ri
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// ext_adddr_sel external addres select; data pointer or Ri
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// write_p output from decoder; write to external ram, go to register;
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// write_p output from decoder; write to external ram, go to register;
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wire [1:0] src_sel1_r, src_sel2_r, cy_sel, cy_sel_r, bank_sel;
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wire [1:0] cy_sel, bank_sel;
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wire src_sel3, src_sel3_r, rom_addr_sel, ext_addr_sel, rmw, ea_int, wr_xaddr;
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wire rom_addr_sel, rmw, ea_int;
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//
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//
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// int_uart interrupt from uart
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// int_uart interrupt from uart
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// tf0 interrupt from t/c 0
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// tf0 interrupt from t/c 0
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// tf1 interrupt from t/c 1
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// tf1 interrupt from t/c 1
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| Line 155... |
Line 152... |
wire reti, intr, int_ack, istb;
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wire reti, intr, int_ack, istb;
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wire [7:0] int_src;
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wire [7:0] int_src;
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//
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//
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//alu_op alu operation (from decoder)
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//alu_op alu operation (from decoder)
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//alu_op_r alu operation (registerd)
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//psw_set write to psw or not; from decoder to psw (through register)
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//psw_set write to psw or not; from decoder to psw (through register)
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wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
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wire mem_wait;
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wire [2:0] mem_act;
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wire [3:0] alu_op;
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wire [1:0] psw_set;
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//
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//
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// immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate2_r from imediate_sel1 to alu_src2_sel1
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// immediate2_r from imediate_sel1 to alu_src2_sel1
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// src1. src2, src2 alu sources
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// src1. src2, src2 alu sources
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// des2, des2 alu destinations
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// des2, des2 alu destinations
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// des1_r destination 1 registerd (to comp1)
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// des1_r destination 1 registerd (to comp1)
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// desCy carry out
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// desCy carry out
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// desAc
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// desAc
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// desOv overflow
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// desOv overflow
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// wr, wr_r write to data ram
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// wr write to data ram
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wire [7:0] src1, src2, src3, des1, des2, des1_r;
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wire [7:0] src1, src2, des1, des2, des1_r;
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wire desCy, desAc, desOv, alu_cy, wr, wr_r;
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wire [7:0] src3;
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wire [7:0] immediate1_r, immediate2_r;
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wire desCy, desAc, desOv, alu_cy, wr, wr_o;
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//
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//
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// rd read program rom
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// rd read program rom
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// pc_wr_sel program counter write select (from decoder to pc)
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// pc_wr_sel program counter write select (from decoder to pc)
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wire rd, pc_wr;
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wire rd, pc_wr;
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wire [1:0] pc_wr_sel;
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wire [2:0] pc_wr_sel;
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//
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//
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// op1_n from op_select to decoder
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// op1_n from op_select to decoder
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// op2_n, output of op_select, to immediate_sel1, pc1, comp1
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// op2_n, output of op_select, to immediate_sel1, pc1, comp1
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// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
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// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
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// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
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// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
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wire [7:0] op1_n, op2_n, op2_dr, op3_n, pc_hi_r;
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wire [7:0] op1_n, op2_n, op3_n;
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//wire [2:0] op1_r;
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//
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//
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// comp_sel select source1 and source2 to compare
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// comp_sel select source1 and source2 to compare
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// eq result (from comp1 to decoder)
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// eq result (from comp1 to decoder)
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// wad2, wad2_r write to accumulator from destination 2
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wire [1:0] comp_sel;
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wire [1:0] comp_sel;
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wire eq, wad2, wad2_r, nop, srcAc, cy, rd_ind, wr_ind;
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wire eq, srcAc, cy, rd_ind, wr_ind;
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wire [2:0] op1_cur;
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//
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//
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// bit_addr bit addresable instruction
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// bit_addr bit addresable instruction
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// bit_data bit data from ram to ram_select
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// bit_data bit data from ram to ram_select
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// bit_out bit data from ram_select to alu and cy_select
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// bit_out bit data from ram_select to alu and cy_select
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wire bit_addr, bit_data, bit_out, bit_addr_r;
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wire bit_addr, bit_data, bit_out, bit_addr_o;
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//
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//
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wire pc_wait;
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//
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//registers
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oc8051_reg8 oc8051_reg8_pc_hi(.clk(clk), .rst(rst), .din(pc[15:8]), .dout(pc_hi_r));
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oc8051_reg2 oc8051_reg2_src_sel1(.clk(clk), .rst(rst), .din(src_sel1), .dout(src_sel1_r));
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oc8051_reg2 oc8051_reg2_src_sel2(.clk(clk), .rst(rst), .din(src_sel2), .dout(src_sel2_r));
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oc8051_reg1 oc8051_reg1_sre_sel3(.clk(clk), .rst(rst), .din(src_sel3), .dout(src_sel3_r));
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oc8051_reg1 oc8051_reg1_wr (.clk(clk), .rst(rst), .din(wr), .dout(wr_r));
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oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
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oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
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oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
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oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
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oc8051_reg2 oc8051_psw_reg (.clk(clk), .rst(rst), .din(psw_set), .dout(psw_set_r));
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oc8051_reg8 oc8051_reg8_rd_ram (.clk(clk), .rst(rst), .din(rd_addr), .dout(rd_addr_r));
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//
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|
//program counter
|
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oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
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.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
|
|
.rd((pc_wait && !(istb_o && !iack_i))), .intr(intr));
|
|
|
|
//
|
//
|
// decoder
|
// decoder
|
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n),
|
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n), .op1_c(op1_cur),
|
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
|
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
|
.src_sel1(src_sel1), .wr_xaddr(wr_xaddr), .src_sel2(src_sel2),
|
.src_sel1(src_sel1), .src_sel2(src_sel2),
|
.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
|
.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
|
.cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
|
.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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.rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
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.wr_sfr(wr_sfr), .rd(rd), .rmw(rmw),
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.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw),
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.istb(istb), .mem_act(mem_act), .mem_wait(mem_wait));
|
.stb_o(stb_o), .ack_i(ack_i), .istb(istb), .ea(ea && ea_int),
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.iack(iack_i), .pc_wait(pc_wait), .nop(nop));
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|
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|
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|
//
|
|
// internal ram address select
|
|
oc8051_ram_adr_sel oc8051_ram_rd_sel1 (.rst(rst), .clk(clk), .rd_sel(ram_rd_sel),
|
|
.wr_sel(ram_wr_sel), .sp(sp), .ri(ri), .rn({bank_sel, op1_n[2:0]}), .imm(op2_dr),
|
|
.imm2(op3_n), .rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind));
|
|
|
|
|
|
|
|
//
|
//
|
//alu
|
//alu
|
oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op_r), .src1(src1), .src2(src2), .src3(src3),
|
oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op), .rd(rd),
|
.srcCy(alu_cy), .srcAc(srcAc), .des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
|
.src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
|
|
.des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
|
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
|
.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
|
|
|
|
|
//
|
|
//
|
|
oc8051_immediate_sel oc8051_immediate_sel1(.clk(clk), .rst(rst), .sel(imm_sel), .op1(op1_n), .op2(op2_n),
|
|
.op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1_r), .out2(immediate2_r));
|
|
|
|
//
|
//
|
//data ram
|
//data ram
|
oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
|
oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
|
.wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r && (!wr_addr[7] || wr_ind)),
|
.wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
|
.bit_data_in(desCy), .bit_data_out(bit_data));
|
.bit_data_in(desCy), .bit_data_out(bit_data));
|
|
|
//
|
//
|
//
|
|
oc8051_alu_src1_sel oc8051_alu_src1_sel1(.sel(src_sel1_r), .immediate(immediate1_r),
|
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(clk), .rst(rst), .rd(rd),
|
.acc(acc), .ram(ram_out), .ext(dat_i), .des(src1));
|
.sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
|
oc8051_alu_src2_sel oc8051_alu_src2_sel1(.sel(src_sel2_r), .immediate(immediate2_r),
|
.acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
|
.acc(acc), .ram(ram_out), .des(src2));
|
.op1(op1_n), .op2(op2_n), .op3(op3_n),
|
oc8051_alu_src3_sel oc8051_alu_src3_sel1(.sel(src_sel3_r), .pc(pc_hi_r),
|
.src1(src1), .src2(src2), .src3(src3));
|
.dptr(dptr_hi), .des(src3));
|
|
|
|
//
|
//
|
//
|
//
|
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
|
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
|
|
|
| Line 296... |
Line 250... |
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
|
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
|
|
//
|
//
|
//
|
//
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel_r), .cy_in(cy), .data_in(bit_out),
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
|
.data_out(alu_cy));
|
.data_out(alu_cy));
|
//
|
//
|
//
|
//
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr),
|
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .rd_addr(rd_addr), .wr_addr(wr_addr),
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri),
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.data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
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.sel(op1_n[0]), .bank(bank_sel));
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.ri_out(ri), .sel(op1_cur), .bank(bank_sel));
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|
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//
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//
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oc8051_rom_addr_sel oc8051_rom_addr_sel1(.clk(clk), .rst(rst), .iack_i(iack_i),
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.ea(ea && ea_int), .sel(rom_addr_sel), .des1(des1), .des2(des2),
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.pc(pc), .out_addr(iadr_o));
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|
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//
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//
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//
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//
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oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
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oc8051_memory_interface oc8051_memory_interface1(.clk(clk), .rst(rst),
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.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o),
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.wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
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.wr(wr_xaddr), .stb(stb_o));
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//rom_addr_sel
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//
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.iack_i(iack_i), .des1(des1), .des2(des2),
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//
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.iadr_o(iadr_o), .sp_w(sp_w),
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oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data), .rd_ind(rd_ind),
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.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .out_data(ram_out));
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//ext_addr_sel
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.dptr({dptr_hi, dptr_lo}), .ri(ri), .rn_mem(rn_mem), .dadr_o(dadr_o), .ddat_o(ddat_o),
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.dwe_o(dwe_o), .dstb_o(dstb_o), .ddat_i(ddat_i), .acc(acc), .dack_i(dack_i),
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|
|
|
//ram_addr_sel
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.rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .sp(sp), .rn({bank_sel, op1_n[2:0]}),
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.rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind),
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|
|
|
//op_select
|
|
.ea(ea), .ea_int(ea_int),
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.op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
|
|
.idat_i(idat_i),
|
|
.op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
|
|
.intr(intr), .int_v(int_src), .rd(rd), .int_ack(int_ack), .istb(istb),
|
|
.istb_o(istb_o),
|
|
|
|
//pc
|
|
.pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
|
|
.mem_act(mem_act), .mem_wait(mem_wait),
|
|
.bit_in(bit_data), .in_ram(ram_data),
|
|
.sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
|
|
.reti(reti));
|
|
|
|
|
//
|
//
|
//
|
//
|
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
|
|
.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
|
|
.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
|
|
.intr(intr), .int_v(int_src), .rd(rd), .ack(int_ack), .istb(istb),
|
|
.istb_o(istb_o), .iack_i(iack_i), .nop(nop));
|
|
|
|
|
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
|
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr), .adr1(wr_addr), .dat0(sfr_out),
|
.dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
|
.dat1(des1), .dat2(des2), .we(wr_r && !wr_ind), .bit_in(desCy), .bit_out(sfr_bit), .wr_bit(bit_addr_r),
|
.bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .wr_sfr(wr_sfr),
|
.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
|
|
// acc
|
// acc
|
.wad2(wad2_r), .acc(acc), .rd_x(stb_o && !we_o && ack_i), .xdata(dat_i),
|
.acc(acc),
|
// sp
|
// sp
|
.sp(sp),
|
.sp(sp), .sp_w(sp_w),
|
// psw
|
// psw
|
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set_r),
|
.bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
|
.srcAc(srcAc), .cy(cy),
|
.srcAc(srcAc), .cy(cy),
|
// ports
|
// ports
|
.rmw(rmw), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
|
.rmw(rmw), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
|
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
|
.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
|
// uart
|
// uart
|
.rxd(rxd), .txd(txd),
|
.rxd(rxd), .txd(txd),
|
// int
|
// int
|
.int_ack(int_ack), .intr(intr), .int0(int0), .int1(int1), .reti(reti), .int_src(int_src),
|
.int_ack(int_ack), .intr(intr), .int0(int0), .int1(int1), .reti(reti), .int_src(int_src),
|
// t/c
|
// t/c
|
.t0(t0), .t1(t1),
|
.t0(t0), .t1(t1), .t2(t2), .t2ex(t2ex),
|
// dptr
|
// dptr
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
|
|
|
|
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
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