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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2003/04/16 10:02:45 simont
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// fix bug (cyc_o and stb_o)
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//
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// Revision 1.3 2003/04/03 19:19:02 simont
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// Revision 1.3 2003/04/03 19:19:02 simont
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// change adr_i and adr_o length.
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// change adr_i and adr_o length.
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//
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//
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// Revision 1.2 2003/01/13 14:14:41 simont
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// Revision 1.2 2003/01/13 14:14:41 simont
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// replace some modules
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// replace some modules
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Line 62... |
// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_wb_iinterface(rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
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module oc8051_wb_iinterface(rst, clk,
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dat_i, cyc_o, adr_o, ack_i, stb_o);
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adr_i, dat_o, cyc_i, stb_i, ack_o,
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adr_o, dat_i, cyc_o, stb_o, ack_i
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);
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//
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//
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// rst (in) reset - pin
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// rst (in) reset - pin
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// clk (in) clock - pini
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// clk (in) clock - pini
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input rst, clk;
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input rst, clk;
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| Line 74... |
Line 79... |
// adr_i (in) address
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// adr_i (in) address
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// dat_o (out) data output
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// dat_o (out) data output
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// stb_i (in) strobe
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// stb_i (in) strobe
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// ack_o (out) acknowledge
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// ack_o (out) acknowledge
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// cyc_i (in) cycle
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// cyc_i (in) cycle
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input stb_i, cyc_i;
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input stb_i,
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cyc_i;
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input [15:0] adr_i;
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input [15:0] adr_i;
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output ack_o;
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output ack_o;
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output [31:0] dat_o;
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output [31:0] dat_o;
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//
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//
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Line 95... |
// stb_o (out) strobe
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// stb_o (out) strobe
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// ack_i (in) acknowledge
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// ack_i (in) acknowledge
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// cyc_o (out) cycle
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// cyc_o (out) cycle
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input ack_i;
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input ack_i;
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input [31:0] dat_i;
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input [31:0] dat_i;
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output stb_o, cyc_o;
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output stb_o,
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cyc_o;
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output [15:0] adr_o;
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output [15:0] adr_o;
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//
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//
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// internal bufers and wires
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// internal bufers and wires
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//
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//
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reg [15:0] adr;
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reg [15:0] adr_o;
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//reg stb;
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reg stb_o;
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assign ack_o = ack_i;
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assign ack_o = ack_i;
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assign dat_o = dat_i;
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assign dat_o = dat_i;
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assign stb_o = stb_i || ack_i;
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//assign stb_o = stb_i || ack_i;
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assign cyc_o = stb_i || ack_i;
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assign cyc_o = stb_o;
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assign adr_o = ack_i ? adr : adr_i;
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//assign adr_o = ack_i ? adr : adr_i;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst) begin
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if (rst) begin
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// stb <= #1 1'b0;
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stb_o <= #1 1'b0;
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adr <= #1 16'h0000;
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adr_o <= #1 16'h0000;
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end else begin
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end else if (ack_i) begin
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// stb <= #1 stb_i;
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stb_o <= #1 1'b0;
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adr <= #1 adr_i;
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end else if (!stb_o & stb_i) begin
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stb_o <= #1 1'b1;
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adr_o <= #1 adr_i;
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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