| Line 12... |
Line 12... |
// Altera or its authorized distributors. Please refer to the
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// Altera or its authorized distributors. Please refer to the
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// applicable agreement for further details.
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// applicable agreement for further details.
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|
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// PROGRAM "Quartus II 64-Bit"
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// PROGRAM "Quartus II 64-Bit"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
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// CREATED "Tue Feb 23 22:17:29 2016"
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// CREATED "Fri Dec 09 21:55:51 2016"
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|
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module alu_flags(
|
module alu_flags(
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ctl_flags_oe,
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ctl_flags_oe,
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ctl_flags_bus,
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ctl_flags_bus,
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ctl_flags_alu,
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ctl_flags_alu,
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| Line 44... |
Line 44... |
ctl_flags_nf_clr,
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ctl_flags_nf_clr,
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ctl_alu_zero_16bit,
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ctl_alu_zero_16bit,
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clk,
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clk,
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ctl_flags_cf2_sel_shift,
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ctl_flags_cf2_sel_shift,
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ctl_flags_cf2_sel_daa,
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ctl_flags_cf2_sel_daa,
|
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hold_clk_wait,
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flags_sf,
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flags_sf,
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flags_zf,
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flags_zf,
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flags_hf,
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flags_hf,
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flags_pf,
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flags_pf,
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flags_cf,
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flags_cf,
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| Line 85... |
Line 86... |
input wire ctl_flags_nf_clr;
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input wire ctl_flags_nf_clr;
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input wire ctl_alu_zero_16bit;
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input wire ctl_alu_zero_16bit;
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input wire clk;
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input wire clk;
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input wire ctl_flags_cf2_sel_shift;
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input wire ctl_flags_cf2_sel_shift;
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input wire ctl_flags_cf2_sel_daa;
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input wire ctl_flags_cf2_sel_daa;
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input wire hold_clk_wait;
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output wire flags_sf;
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output wire flags_sf;
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output wire flags_zf;
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output wire flags_zf;
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output wire flags_hf;
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output wire flags_hf;
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output wire flags_pf;
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output wire flags_pf;
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output wire flags_cf;
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output wire flags_cf;
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| Line 98... |
Line 100... |
inout wire [7:0] db;
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inout wire [7:0] db;
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|
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reg flags_xf;
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reg flags_xf;
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reg flags_yf;
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reg flags_yf;
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wire [1:0] sel;
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wire [1:0] sel;
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wire SYNTHESIZED_WIRE_0;
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reg DFFE_inst_latch_hf;
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reg DFFE_inst_latch_hf;
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wire SYNTHESIZED_WIRE_0;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_1;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_2;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_3;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_4;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_5;
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wire SYNTHESIZED_WIRE_6;
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wire SYNTHESIZED_WIRE_6;
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wire SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_7;
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wire SYNTHESIZED_WIRE_8;
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reg SYNTHESIZED_WIRE_41;
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reg SYNTHESIZED_WIRE_38;
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wire SYNTHESIZED_WIRE_42;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_9;
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wire SYNTHESIZED_WIRE_10;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_11;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_12;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_13;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_14;
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wire SYNTHESIZED_WIRE_15;
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wire SYNTHESIZED_WIRE_15;
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| Line 123... |
Line 124... |
wire SYNTHESIZED_WIRE_18;
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wire SYNTHESIZED_WIRE_18;
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wire SYNTHESIZED_WIRE_19;
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wire SYNTHESIZED_WIRE_19;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_20;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_21;
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wire SYNTHESIZED_WIRE_22;
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wire SYNTHESIZED_WIRE_22;
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reg DFFE_inst_latch_sf;
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wire SYNTHESIZED_WIRE_23;
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wire SYNTHESIZED_WIRE_23;
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reg DFFE_inst_latch_pf;
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reg DFFE_inst_latch_nf;
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wire SYNTHESIZED_WIRE_24;
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wire SYNTHESIZED_WIRE_24;
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reg DFFE_inst_latch_sf;
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wire SYNTHESIZED_WIRE_25;
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wire SYNTHESIZED_WIRE_25;
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reg DFFE_inst_latch_pf;
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reg DFFE_inst_latch_nf;
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wire SYNTHESIZED_WIRE_26;
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wire SYNTHESIZED_WIRE_26;
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wire SYNTHESIZED_WIRE_27;
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wire SYNTHESIZED_WIRE_27;
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wire SYNTHESIZED_WIRE_28;
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wire SYNTHESIZED_WIRE_28;
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wire SYNTHESIZED_WIRE_39;
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wire SYNTHESIZED_WIRE_29;
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wire SYNTHESIZED_WIRE_30;
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wire SYNTHESIZED_WIRE_31;
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wire SYNTHESIZED_WIRE_31;
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wire SYNTHESIZED_WIRE_32;
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wire SYNTHESIZED_WIRE_43;
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wire SYNTHESIZED_WIRE_33;
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wire SYNTHESIZED_WIRE_34;
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wire SYNTHESIZED_WIRE_34;
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wire SYNTHESIZED_WIRE_35;
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wire SYNTHESIZED_WIRE_35;
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wire SYNTHESIZED_WIRE_36;
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wire SYNTHESIZED_WIRE_36;
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wire SYNTHESIZED_WIRE_37;
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wire SYNTHESIZED_WIRE_38;
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wire SYNTHESIZED_WIRE_39;
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reg DFFE_inst_latch_cf;
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reg DFFE_inst_latch_cf;
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reg DFFE_inst_latch_cf2;
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reg DFFE_inst_latch_cf2;
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wire SYNTHESIZED_WIRE_37;
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wire SYNTHESIZED_WIRE_40;
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assign flags_sf = DFFE_inst_latch_sf;
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assign flags_sf = DFFE_inst_latch_sf;
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assign flags_zf = SYNTHESIZED_WIRE_38;
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assign flags_zf = SYNTHESIZED_WIRE_41;
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assign flags_hf = SYNTHESIZED_WIRE_23;
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assign flags_hf = SYNTHESIZED_WIRE_25;
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assign flags_pf = DFFE_inst_latch_pf;
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assign flags_pf = DFFE_inst_latch_pf;
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assign flags_cf = SYNTHESIZED_WIRE_24;
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assign flags_cf = SYNTHESIZED_WIRE_26;
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assign flags_nf = DFFE_inst_latch_nf;
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assign flags_nf = DFFE_inst_latch_nf;
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assign flags_cf_latch = DFFE_inst_latch_cf;
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assign flags_cf_latch = DFFE_inst_latch_cf;
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assign SYNTHESIZED_WIRE_37 = 0;
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assign SYNTHESIZED_WIRE_40 = 0;
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assign SYNTHESIZED_WIRE_12 = db[7] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_19 = alu_xf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_27 = ctl_flags_cf_we & SYNTHESIZED_WIRE_0;
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assign SYNTHESIZED_WIRE_22 = db[2] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_10 = db[7] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_21 = pf_sel & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_17 = alu_xf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_20 = db[2] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_25 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
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assign SYNTHESIZED_WIRE_19 = pf_sel & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_24 = db[0] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_3 = db[1] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_23 = ctl_flags_alu & alu_core_cf_out;
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assign SYNTHESIZED_WIRE_23 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
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assign SYNTHESIZED_WIRE_9 = ~ctl_flags_cf2_we;
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assign SYNTHESIZED_WIRE_22 = db[0] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
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assign SYNTHESIZED_WIRE_21 = ctl_flags_alu & alu_core_cf_out;
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assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_0 = ~ctl_flags_cf2_we;
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assign SYNTHESIZED_WIRE_11 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_1 ^ ctl_flags_cf_cpl;
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assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
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assign SYNTHESIZED_WIRE_2 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
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assign SYNTHESIZED_WIRE_9 = alu_sf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_6 = ctl_flags_nf_set | SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
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assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
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assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_4 & SYNTHESIZED_WIRE_5;
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assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;
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assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;
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assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7;
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assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_41;
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assign SYNTHESIZED_WIRE_7 = ~ctl_flags_nf_clr;
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assign SYNTHESIZED_WIRE_42 = ~hold_clk_wait;
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assign SYNTHESIZED_WIRE_8 = ~ctl_alu_zero_16bit;
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assign SYNTHESIZED_WIRE_29 = ctl_flags_cf_we & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_9;
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assign SYNTHESIZED_WIRE_5 = SYNTHESIZED_WIRE_8 | SYNTHESIZED_WIRE_38;
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assign SYNTHESIZED_WIRE_31 = ctl_flags_cf2_we & SYNTHESIZED_WIRE_42;
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assign SYNTHESIZED_WIRE_12 = db[6] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_14 = db[6] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_33 = SYNTHESIZED_WIRE_9 | SYNTHESIZED_WIRE_10;
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assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
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assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
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assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
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assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
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assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
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assign SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
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assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
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assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
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assign SYNTHESIZED_WIRE_32 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
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assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
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assign SYNTHESIZED_WIRE_11 = alu_zero & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_13 = alu_zero & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
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assign SYNTHESIZED_WIRE_28 = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24;
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assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
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assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
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assign SYNTHESIZED_WIRE_14 = db[5] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_16 = db[5] & ctl_flags_bus;
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assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_38 : 1'bz;
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assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_41 : 1'bz;
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assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
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assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;
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assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_23 : 1'bz;
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assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_25 : 1'bz;
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assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
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assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;
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assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
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assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
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assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
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assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
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assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_24 : 1'bz;
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assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_26 : 1'bz;
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assign SYNTHESIZED_WIRE_13 = alu_yf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_15 = alu_yf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_1 = ctl_flags_cf_set | SYNTHESIZED_WIRE_25;
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assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_27;
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assign SYNTHESIZED_WIRE_16 = db[4] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_18 = db[4] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_15 = alu_core_cf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_17 = alu_core_cf_out & ctl_flags_alu;
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assign SYNTHESIZED_WIRE_18 = db[3] & ctl_flags_bus;
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assign SYNTHESIZED_WIRE_20 = db[3] & ctl_flags_bus;
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always@(posedge clk)
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always@(posedge clk)
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begin
|
begin
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if (SYNTHESIZED_WIRE_27)
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if (SYNTHESIZED_WIRE_29)
|
begin
|
begin
|
DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_26;
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DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_28;
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end
|
end
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end
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end
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|
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always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
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if (ctl_flags_cf2_we)
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if (SYNTHESIZED_WIRE_31)
|
begin
|
begin
|
DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_28;
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DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_30;
|
end
|
end
|
end
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end
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|
|
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always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_hf_we)
|
if (ctl_flags_hf_we)
|
begin
|
begin
|
DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_39;
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DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_43;
|
end
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end
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end
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end
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|
|
|
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always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_hf2_we)
|
if (ctl_flags_hf2_we)
|
begin
|
begin
|
flags_hf2 <= SYNTHESIZED_WIRE_39;
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flags_hf2 <= SYNTHESIZED_WIRE_43;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_nf_we)
|
if (ctl_flags_nf_we)
|
begin
|
begin
|
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_31;
|
DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_34;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_pf_we)
|
if (ctl_flags_pf_we)
|
begin
|
begin
|
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_32;
|
DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_35;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_sz_we)
|
if (ctl_flags_sz_we)
|
begin
|
begin
|
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_33;
|
DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_36;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_xy_we)
|
if (ctl_flags_xy_we)
|
begin
|
begin
|
flags_xf <= SYNTHESIZED_WIRE_34;
|
flags_xf <= SYNTHESIZED_WIRE_37;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_xy_we)
|
if (ctl_flags_xy_we)
|
begin
|
begin
|
flags_yf <= SYNTHESIZED_WIRE_35;
|
flags_yf <= SYNTHESIZED_WIRE_38;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge clk)
|
always@(posedge clk)
|
begin
|
begin
|
if (ctl_flags_sz_we)
|
if (ctl_flags_sz_we)
|
begin
|
begin
|
SYNTHESIZED_WIRE_38 <= SYNTHESIZED_WIRE_36;
|
SYNTHESIZED_WIRE_41 <= SYNTHESIZED_WIRE_39;
|
end
|
end
|
end
|
end
|
|
|
|
|
alu_mux_2 b2v_inst_mux_cf(
|
alu_mux_2 b2v_inst_mux_cf(
|
.in0(DFFE_inst_latch_cf),
|
.in0(DFFE_inst_latch_cf),
|
.in1(DFFE_inst_latch_cf2),
|
.in1(DFFE_inst_latch_cf2),
|
.sel1(ctl_flags_use_cf2),
|
.sel1(ctl_flags_use_cf2),
|
.out(SYNTHESIZED_WIRE_25));
|
.out(SYNTHESIZED_WIRE_27));
|
|
|
|
|
alu_mux_4 b2v_inst_mux_cf2(
|
alu_mux_4 b2v_inst_mux_cf2(
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.in0(alu_core_cf_out),
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.in0(alu_core_cf_out),
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.in1(shift_cf_out),
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.in1(shift_cf_out),
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.in2(daa_cf_out),
|
.in2(daa_cf_out),
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.in3(SYNTHESIZED_WIRE_37),
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.in3(SYNTHESIZED_WIRE_40),
|
.sel(sel),
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.sel(sel),
|
.out(SYNTHESIZED_WIRE_28));
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.out(SYNTHESIZED_WIRE_30));
|
|
|
assign sel[0] = ctl_flags_cf2_sel_shift;
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assign sel[0] = ctl_flags_cf2_sel_shift;
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assign sel[1] = ctl_flags_cf2_sel_daa;
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assign sel[1] = ctl_flags_cf2_sel_daa;
|
|
|
endmodule
|
endmodule
|
