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https://opencores.org/ocsvn/a-z80/a-z80/trunk
[/] [a-z80/] [trunk/] [cpu/] [export.py] - Diff between revs 17 and 19
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Rev 19 |
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#!/usr/bin/env python3
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#!/usr/bin/env python3
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#
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#
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# This script exports all core A-Z80 Verilog files to a destination folder of your choice.
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# Run this script to export necessary CPU files away and into your project.
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# Add all Verilog files (*.v) to your project and ensure that Verilog include files (*.vh)
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# are on the include path.
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#
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#
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#-------------------------------------------------------------------------------
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#-------------------------------------------------------------------------------
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# Copyright (C) 2014,2017 Goran Devic, www.baltazarstudios.com
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# Copyright (C) 2014,2018 Goran Devic, www.baltazarstudios.com
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#
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#
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# This program is free software; you can redistribute it and/or modify it
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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# under the terms of the GNU General Public License as published by the Free
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# Software Foundation; either version 2 of the License, or (at your option)
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# Software Foundation; either version 2 of the License, or (at your option)
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# any later version.
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# any later version.
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import os
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import os
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from shutil import copyfile
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from shutil import copyfile
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if len(sys.argv) != 2:
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if len(sys.argv) != 2:
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print ("\nUsage: export.py <destination-folder>\n")
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print ("\nUsage: export.py <destination-folder>\n")
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print ("Copies all core A-Z80 Verilog files to a destination folder of your choice.")
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print ("Exports all necessary A-Z80 Verilog files to a project folder of your choice.")
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exit(-1)
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exit(-1)
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dest = sys.argv[1]
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dest = sys.argv[1]
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total = 0
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total = 0
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