| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: xsv_fpga_top.v,v $
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// $Log: xsv_fpga_top.v,v $
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// Revision 1.6 2011-02-14 04:16:25 natey
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// Major functionality enhancement - now duplicates the full OR1K self-test performed by adv_jtag_bridge.
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//
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// Revision 1.5 2010-01-16 02:15:22 Nathan
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// Revision 1.5 2010-01-16 02:15:22 Nathan
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// Updated to match changes in hardware. Added support for hi-speed mode.
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// Updated to match changes in hardware. Added support for hi-speed mode.
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//
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//
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// Revision 1.4 2010-01-08 01:41:07 Nathan
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// Revision 1.4 2010-01-08 01:41:07 Nathan
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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// Removed unused, non-existant include from CPU behavioral model. Minor text edits.
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| Line 144... |
Line 147... |
wire [31:0] wb_dm_dat_o;
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wire [31:0] wb_dm_dat_o;
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wire [3:0] wb_dm_sel_o;
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wire [3:0] wb_dm_sel_o;
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wire wb_dm_we_o;
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wire wb_dm_we_o;
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wire wb_dm_stb_o;
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wire wb_dm_stb_o;
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wire wb_dm_cyc_o;
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wire wb_dm_cyc_o;
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wire wb_dm_cab_o;
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wire wb_dm_ack_i;
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wire wb_dm_ack_i;
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wire wb_dm_err_i;
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wire wb_dm_err_i;
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//
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//
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// Debug <-> RISC wires
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// Debug <-> RISC wires
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| Line 191... |
Line 193... |
wire wb_rim_ack_i;
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wire wb_rim_ack_i;
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wire wb_rim_err_i;
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wire wb_rim_err_i;
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wire wb_rim_rty_i = 1'b0;
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wire wb_rim_rty_i = 1'b0;
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wire wb_rim_we_o;
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wire wb_rim_we_o;
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wire wb_rim_stb_o;
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wire wb_rim_stb_o;
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wire wb_rim_cab_o;
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//wire [31:0] wb_rif_adr;
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//wire [31:0] wb_rif_adr;
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//reg prefix_flash;
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//reg prefix_flash;
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//
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//
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// RISC data master i/f wires
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// RISC data master i/f wires
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| Line 208... |
Line 209... |
wire wb_rdm_ack_i;
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wire wb_rdm_ack_i;
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wire wb_rdm_err_i;
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wire wb_rdm_err_i;
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wire wb_rdm_rty_i = 1'b0;
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wire wb_rdm_rty_i = 1'b0;
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wire wb_rdm_we_o;
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wire wb_rdm_we_o;
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wire wb_rdm_stb_o;
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wire wb_rdm_stb_o;
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wire wb_rdm_cab_o;
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//
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//
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// RISC misc
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// RISC misc
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//
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//
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//wire [19:0] pic_ints;
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//wire [19:0] pic_ints;
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| Line 525... |
Line 525... |
.iwb_ack_i ( wb_rim_ack_i ),
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.iwb_ack_i ( wb_rim_ack_i ),
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.iwb_err_i ( wb_rim_err_i ),
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.iwb_err_i ( wb_rim_err_i ),
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.iwb_rty_i ( wb_rim_rty_i ),
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.iwb_rty_i ( wb_rim_rty_i ),
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.iwb_we_o ( wb_rim_we_o ),
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.iwb_we_o ( wb_rim_we_o ),
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.iwb_stb_o ( wb_rim_stb_o ),
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.iwb_stb_o ( wb_rim_stb_o ),
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.iwb_cab_o ( wb_rim_cab_o ),
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// WISHBONE Data Master
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// WISHBONE Data Master
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.dwb_clk_i ( wb_clk ),
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.dwb_clk_i ( wb_clk ),
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.dwb_rst_i ( wb_rst ),
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.dwb_rst_i ( wb_rst ),
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.dwb_cyc_o ( wb_rdm_cyc_o ),
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.dwb_cyc_o ( wb_rdm_cyc_o ),
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| Line 540... |
Line 539... |
.dwb_ack_i ( wb_rdm_ack_i ),
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.dwb_ack_i ( wb_rdm_ack_i ),
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.dwb_err_i ( wb_rdm_err_i ),
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.dwb_err_i ( wb_rdm_err_i ),
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.dwb_rty_i ( wb_rdm_rty_i ),
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.dwb_rty_i ( wb_rdm_rty_i ),
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.dwb_we_o ( wb_rdm_we_o ),
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.dwb_we_o ( wb_rdm_we_o ),
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.dwb_stb_o ( wb_rdm_stb_o ),
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.dwb_stb_o ( wb_rdm_stb_o ),
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.dwb_cab_o ( wb_rdm_cab_o ),
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// Debug
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// Debug
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.dbg_stall_i ( dbg_stall ), // Set to 1'b0 if debug is absent / broken
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.dbg_stall_i ( dbg_stall ), // Set to 1'b0 if debug is absent / broken
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_adr_i ( dbg_adr ),
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.dbg_adr_i ( dbg_adr ),
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| Line 731... |
Line 729... |
.m2_err_o ( ),
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.m2_err_o ( ),
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// WISHBONE Initiator 3
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// WISHBONE Initiator 3
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.m3_cyc_i ( wb_dm_cyc_o ),
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.m3_cyc_i ( wb_dm_cyc_o ),
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.m3_stb_i ( wb_dm_stb_o ),
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.m3_stb_i ( wb_dm_stb_o ),
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.m3_cab_i ( wb_dm_cab_o ),
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.m3_cab_i ( 1'b0 ),
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.m3_adr_i ( wb_dm_adr_o ),
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.m3_adr_i ( wb_dm_adr_o ),
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.m3_sel_i ( wb_dm_sel_o ),
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.m3_sel_i ( wb_dm_sel_o ),
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.m3_we_i ( wb_dm_we_o ),
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.m3_we_i ( wb_dm_we_o ),
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.m3_dat_i ( wb_dm_dat_o ),
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.m3_dat_i ( wb_dm_dat_o ),
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.m3_dat_o ( wb_dm_dat_i ),
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.m3_dat_o ( wb_dm_dat_i ),
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| Line 743... |
Line 741... |
.m3_err_o ( wb_dm_err_i ),
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.m3_err_o ( wb_dm_err_i ),
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// WISHBONE Initiator 4
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// WISHBONE Initiator 4
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.m4_cyc_i ( wb_rdm_cyc_o ),
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.m4_cyc_i ( wb_rdm_cyc_o ),
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.m4_stb_i ( wb_rdm_stb_o ),
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.m4_stb_i ( wb_rdm_stb_o ),
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.m4_cab_i ( wb_rdm_cab_o ),
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.m4_cab_i ( 1'b0 ),
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.m4_adr_i ( wb_rdm_adr_o ),
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.m4_adr_i ( wb_rdm_adr_o ),
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.m4_sel_i ( wb_rdm_sel_o ),
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.m4_sel_i ( wb_rdm_sel_o ),
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.m4_we_i ( wb_rdm_we_o ),
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.m4_we_i ( wb_rdm_we_o ),
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.m4_dat_i ( wb_rdm_dat_o ),
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.m4_dat_i ( wb_rdm_dat_o ),
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.m4_dat_o ( wb_rdm_dat_i ),
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.m4_dat_o ( wb_rdm_dat_i ),
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| Line 755... |
Line 753... |
.m4_err_o ( wb_rdm_err_i ),
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.m4_err_o ( wb_rdm_err_i ),
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// WISHBONE Initiator 5
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// WISHBONE Initiator 5
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.m5_cyc_i ( wb_rim_cyc_o ),
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.m5_cyc_i ( wb_rim_cyc_o ),
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.m5_stb_i ( wb_rim_stb_o ),
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.m5_stb_i ( wb_rim_stb_o ),
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.m5_cab_i ( wb_rim_cab_o ),
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.m5_cab_i ( 1'b0 ),
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.m5_adr_i ( wb_rim_adr_o ),
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.m5_adr_i ( wb_rim_adr_o ),
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.m5_sel_i ( wb_rim_sel_o ),
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.m5_sel_i ( wb_rim_sel_o ),
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.m5_we_i ( wb_rim_we_o ),
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.m5_we_i ( wb_rim_we_o ),
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.m5_dat_i ( wb_rim_dat_o ),
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.m5_dat_i ( wb_rim_dat_o ),
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.m5_dat_o ( wb_rim_dat_i ),
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.m5_dat_o ( wb_rim_dat_i ),
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