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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adbg_defines.v,v $
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// Revision 1.4 2010-01-14 02:03:40 Nathan
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// Make hi-speed mode the default
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//
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// Revision 1.3 2010-01-10 22:53:48 Nathan
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// Added define for hi-speed mode
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//
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.1 2008/07/22 20:28:30 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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// Revision 1.5 2008/07/06 20:02:53 Nathan
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// Fixes for synthesis with Xilinx ISE (also synthesizable with
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// Quartus II 7.0). Ran through dos2unix.
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//
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// Revision 1.4 2008/06/30 20:09:20 Nathan
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// Removed code to select top-level module as active (it served no
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// purpose). Re-numbered modules, requiring changes to testbench and software driver.
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//
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// Length of the MODULE ID register
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// Length of the MODULE ID register
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`define DBG_TOP_MODULE_ID_LENGTH 2
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`define DBG_TOP_MODULE_ID_LENGTH 2
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// How many modules can be supported by the module id length
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// How many modules can be supported by the module id length
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// Chains
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// Chains
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0
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`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0
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`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1
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`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1
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`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2
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`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2
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`define DBG_TOP_JSP_DEBUG_MODULE 2'h3
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// Length of data
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// Length of data
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`define DBG_TOP_MODULE_DATA_LEN 53
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`define DBG_TOP_MODULE_DATA_LEN 53
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// If WISHBONE sub-module is supported uncomment the folowing line
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// If WISHBONE sub-module is supported uncomment the following line
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`define DBG_WISHBONE_SUPPORTED
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`define DBG_WISHBONE_SUPPORTED
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// If CPU_0 sub-module is supported uncomment the folowing line
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// If CPU_0 sub-module is supported uncomment the following line
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`define DBG_CPU0_SUPPORTED
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`define DBG_CPU0_SUPPORTED
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// If CPU_1 sub-module is supported uncomment the folowing line
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// If CPU_1 sub-module is supported uncomment the following line
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//`define DBG_CPU1_SUPPORTED
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//`define DBG_CPU1_SUPPORTED
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// To include the JTAG Serial Port (JSP), uncomment the following line
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`define DBG_JSP_SUPPORTED
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// Define this if you intend to use the JSP in a system with multiple
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// devices on the JTAG chain
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`define ADBG_JSP_SUPPORT_MULTI
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// If this is defined, status bits will be skipped on burst
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// If this is defined, status bits will be skipped on burst
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// writes to improve download speeds.
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// reads and writes to improve download speeds.
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`define ADBG_USE_HISPEED
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`define ADBG_USE_HISPEED
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No newline at end of file
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No newline at end of file
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