URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_jsp_biu.v] - Diff between revs 42 and 51

Rev 42	Rev 51
Line 510...	Line 510...
`if(wr_fifo_not_empty) iir_gen <= 3'b100;`	`if(wr_fifo_not_empty) iir_gen <= 3'b100;`
`else if(thr_int_arm & rd_fifo_not_full) iir_gen <= 3'b010;`	`else if(thr_int_arm & rd_fifo_not_full) iir_gen <= 3'b010;`
`else iir_gen <= 3'b001;`	`else iir_gen <= 3'b001;`
`end`	`end`

`assign reg_iir = {5'b00000, iir_gen};`	`assign reg_iir = iir_gen;`

`// Create the data lines out to the WB.`	`// Create the data lines out to the WB.`
`// Always put all 4 bytes on the WB data lines, let the master pick out what it`	`// Always put all 4 bytes on the WB data lines, let the master pick out what it`
`// wants.`	`// wants.`
`assign bus_data_lo = {data_to_wb, {4'b0000, reg_ier}, {5'b00000, reg_iir}, reg_lcr};`	`assign bus_data_lo = {data_to_wb, {4'b0000, reg_ier}, {5'b00000, reg_iir}, reg_lcr};`