URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_jsp_module.v] - Diff between revs 42 and 51

Rev 42	Rev 51
Line 352...	Line 352...


`// Outputs of state machine, pure combinatorial`	`// Outputs of state machine, pure combinatorial`
`always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i`	`always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i`
`or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count`	`or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count`
`or decremented_out_word_count)`	`or decremented_out_word_count or user_word_count_zero)`
`begin`	`begin`
`// Default everything to 0, keeps the case statement simple`	`// Default everything to 0, keeps the case statement simple`
`wr_bit_ct_en <= 1'b0; // enable bit counter`	`wr_bit_ct_en <= 1'b0; // enable bit counter`
`wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register`	`wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register`
`in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`	`in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`