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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_or1k_module.v] - Diff between revs 32 and 42

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Rev 32 Rev 42
Line 38... Line 38...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: adbg_or1k_module.v,v $
// $Log: adbg_or1k_module.v,v $
 
// Revision 1.6  2010-03-08 21:04:18  Nathan
 
// Changes for the JTAG serial port module.  Uncompiled, untestede.  Removed CVS logs, minor fixes in comments.
 
//
// Revision 1.5  2010-01-13 00:55:45  Nathan
// Revision 1.5  2010-01-13 00:55:45  Nathan
// Created hi-speed mode for burst reads.  This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
// Created hi-speed mode for burst reads.  This will probably be most beneficial to the OR1K module, as GDB does a burst read of all the GPRs each time a microinstruction is single-stepped.
//
//
// Revision 1.2  2009/05/17 20:54:56  Nathan
// Revision 1.2  2009/05/17 20:54:56  Nathan
// Changed email address to opencores.org
// Changed email address to opencores.org
Line 105... Line 108...
   input [52:0]  data_register_i;
   input [52:0]  data_register_i;
   input         module_select_i;
   input         module_select_i;
   output        top_inhibit_o;
   output        top_inhibit_o;
   input         rst_i;
   input         rst_i;
 
 
   // WISHBONE master interface
   // Interface to OR1200 debug unit
   input         cpu_clk_i;    // 'bus' style interface to SPRs
   input         cpu_clk_i;    // 'bus' style interface to SPRs
   output [31:0] cpu_addr_o;
   output [31:0] cpu_addr_o;
   input [31:0]  cpu_data_i;
   input [31:0]  cpu_data_i;
   output [31:0] cpu_data_o;
   output [31:0] cpu_data_o;
   output        cpu_stb_o;
   output        cpu_stb_o;

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