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Line 34... |
//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: adbg_top.v,v $
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// Revision 1.3 2010-01-10 22:54:11 Nathan
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// Update copyright dates
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//
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// Revision 1.2 2009/05/17 20:54:56 Nathan
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// Changed email address to opencores.org
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//
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// Revision 1.1 2008/07/22 20:28:32 Nathan
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// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
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//
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// Revision 1.10 2008/07/11 08:13:29 Nathan
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// Latch opcode on posedge, like other signals. This fixes a problem
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// when the module is used with a Xilinx BSCAN TAP. Added signals to
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// allow modules to inhibit latching of a new active module by the top
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// module. This allows the sub-modules to force the top level module
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// to ignore the command present in the input shift register after e.g.
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// a burst read.
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//
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// Revision 1.7 2008/06/30 20:09:20 Nathan
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// Removed code to select top-level module as active (it served no
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// purpose). Re-numbered modules, requiring changes to testbench and
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// software driver.
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//
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`include "adbg_defines.v"
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`include "adbg_defines.v"
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| Line 88... |
Line 62... |
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`ifdef DBG_WISHBONE_SUPPORTED
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`ifdef DBG_WISHBONE_SUPPORTED
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// WISHBONE common signals
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// WISHBONE common signals
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,
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,
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wb_clk_i,
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wb_clk_i,
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wb_rst_i,
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// WISHBONE master interface
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// WISHBONE master interface
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wb_adr_o,
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wb_adr_o,
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wb_dat_o,
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wb_dat_o,
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wb_dat_i,
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wb_dat_i,
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| Line 134... |
Line 109... |
cpu1_we_o,
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cpu1_we_o,
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cpu1_ack_i,
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cpu1_ack_i,
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cpu1_rst_o
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cpu1_rst_o
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`endif
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`endif
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`ifdef DBG_JSP_SUPPORTED
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,
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`ifndef DBG_WISHBONE_SUPPORTED
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wb_clk_i,
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wb_rst_i,
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`endif
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// WISHBONE target interface
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wb_jsp_adr_i,
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wb_jsp_dat_o,
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wb_jsp_dat_i,
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wb_jsp_cyc_i,
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wb_jsp_stb_i,
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wb_jsp_sel_i,
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wb_jsp_we_i,
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wb_jsp_ack_o,
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wb_jsp_cab_i,
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wb_jsp_err_o,
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wb_jsp_cti_i,
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wb_jsp_bte_i,
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int_o
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`endif
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);
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);
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// JTAG signals
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// JTAG signals
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input tck_i;
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input tck_i;
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Line 152... |
// Module select from TAP
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// Module select from TAP
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input debug_select_i;
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input debug_select_i;
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`ifdef DBG_WISHBONE_SUPPORTED
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`ifdef DBG_WISHBONE_SUPPORTED
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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output [31:0] wb_adr_o;
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output [31:0] wb_adr_o;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output wb_cyc_o;
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output wb_cyc_o;
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output wb_stb_o;
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output wb_stb_o;
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| Line 195... |
Line 194... |
output cpu1_we_o;
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output cpu1_we_o;
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input cpu1_ack_i;
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input cpu1_ack_i;
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output cpu1_rst_o;
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output cpu1_rst_o;
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`endif
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`endif
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`ifdef DBG_JSP_SUPPORTED
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`ifndef DBG_WISHBONE_SUPPORTED
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input wb_clk_i;
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input wb_rst_i;
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`endif
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input [31:0] wb_jsp_adr_i;
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output [31:0] wb_jsp_dat_o;
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input [31:0] wb_jsp_dat_i;
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input wb_jsp_cyc_i;
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input wb_jsp_stb_i;
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input [3:0] wb_jsp_sel_i;
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input wb_jsp_we_i;
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output wb_jsp_ack_o;
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input wb_jsp_cab_i;
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output wb_jsp_err_o;
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input [2:0] wb_jsp_cti_i;
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input [1:0] wb_jsp_bte_i;
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output int_o;
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`endif
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reg tdo_o;
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reg tdo_o;
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wire tdo_wb;
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wire tdo_wb;
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wire tdo_cpu0;
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wire tdo_cpu0;
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wire tdo_cpu1;
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wire tdo_cpu1;
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wire tdo_jsp;
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// Registers
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// Registers
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reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
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reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
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//reg output_shift_reg; // Just 1 bit for status (valid module selected)
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//reg output_shift_reg; // Just 1 bit for status (valid module selected)
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reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
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reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
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Line 231... |
// Control signals
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// Control signals
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wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection
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wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection
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wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
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wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
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reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
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reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
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wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID
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wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID
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wire [2:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
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wire [3:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID
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///////////////////////////////////////
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///////////////////////////////////////
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// Combinatorial assignments
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// Combinatorial assignments
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assign select_cmd = input_shift_reg[52];
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assign select_cmd = input_shift_reg[52];
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| Line 334... |
Line 352... |
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`ifdef DBG_CPU1_SUPPORTED
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`ifdef DBG_CPU1_SUPPORTED
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// Connecting cpu module
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// Connecting cpu module
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adbg_or1k_module i_dbg_cpu_8051 (
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adbg_or1k_module i_dbg_cpu_2 (
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// JTAG signals
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// JTAG signals
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.tck_i (tck_i),
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.tck_i (tck_i),
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.module_tdo_o (tdo_cpu1),
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.module_tdo_o (tdo_cpu1),
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.tdi_i (tdi_i),
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.tdi_i (tdi_i),
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| Line 367... |
Line 385... |
`else
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`else
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assign tdo_cpu1 = 1'b0;
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assign tdo_cpu1 = 1'b0;
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assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
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assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
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`endif
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`endif
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`ifdef DBG_JSP_SUPPORTED
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adbg_jsp_module i_dbg_jsp (
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// JTAG signals
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.tck_i (tck_i),
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.module_tdo_o (tdo_jsp),
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.tdi_i (tdi_i),
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// TAP states
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.capture_dr_i (capture_dr_i),
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.shift_dr_i (shift_dr_i),
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.update_dr_i (update_dr_i),
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.data_register_i (input_shift_reg),
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.module_select_i (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
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.top_inhibit_o (module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE]),
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.rst_i (rst_i),
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// WISHBONE common signals
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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// WISHBONE master interface
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.wb_adr_i (wb_jsp_adr_i),
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.wb_dat_o (wb_jsp_dat_o),
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.wb_dat_i (wb_jsp_dat_i),
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.wb_cyc_i (wb_jsp_cyc_i),
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.wb_stb_i (wb_jsp_stb_i),
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.wb_sel_i (wb_jsp_sel_i),
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.wb_we_i (wb_jsp_we_i),
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.wb_ack_o (wb_jsp_ack_o),
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.wb_cab_i (wb_jsp_cab_i),
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.wb_err_o (wb_jsp_err_o),
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.wb_cti_i (wb_jsp_cti_i),
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.wb_bte_i (wb_jsp_bte_i),
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.int_o (int_o)
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);
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`else
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assign tdo_jsp = 1'b0;
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assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
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`endif
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assign select_inhibit = |module_inhibit;
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assign select_inhibit = |module_inhibit;
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/////////////////////////////////////////////////
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/////////////////////////////////////////////////
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// TDO output MUX
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// TDO output MUX
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always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1)
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always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)
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begin
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begin
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case (module_id_reg)
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case (module_id_reg)
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`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
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`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
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`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
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`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
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`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
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`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
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`DBG_TOP_JSP_DEBUG_MODULE: tdo_o <= tdo_jsp;
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default: tdo_o <= 1'b0;
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default: tdo_o <= 1'b0;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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