| Line 38... |
Line 38... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: adbg_wb_biu.v,v $
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// $Log: adbg_wb_biu.v,v $
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// Revision 1.5 2010-03-21 01:05:10 Nathan
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// Use all 32 address bits - WishBone slaves may use the 2 least-significant address bits instead of the four wb_sel lines, or in addition to them.
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//
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// Revision 1.4 2010-01-10 22:54:11 Nathan
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// Revision 1.4 2010-01-10 22:54:11 Nathan
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// Update copyright dates
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// Update copyright dates
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//
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//
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// Revision 1.3 2009/05/17 20:54:57 Nathan
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// Revision 1.3 2009/05/17 20:54:57 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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| Line 133... |
Line 136... |
wire [1:0] wb_bte_o;
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wire [1:0] wb_bte_o;
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// Registers
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// Registers
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reg [3:0] sel_reg;
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reg [3:0] sel_reg;
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reg [29:0] addr_reg; // Don't need the two LSB, this info is in the SEL bits
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reg [31:0] addr_reg; // Don't really need the two LSB, this info is in the SEL bits
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_in_reg; // dbg->WB
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reg [31:0] data_out_reg; // WB->dbg
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reg [31:0] data_out_reg; // WB->dbg
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reg wr_reg;
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reg wr_reg;
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg str_sync; // This is 'active-toggle' rather than -high or -low.
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reg rdy_sync; // ditto, active-toggle
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reg rdy_sync; // ditto, active-toggle
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| Line 237... |
Line 240... |
// Latch input data on 'start' strobe, if ready.
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// Latch input data on 'start' strobe, if ready.
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always @ (posedge tck_i or posedge rst_i)
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always @ (posedge tck_i or posedge rst_i)
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begin
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begin
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if(rst_i) begin
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if(rst_i) begin
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sel_reg <= 4'h0;
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sel_reg <= 4'h0;
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addr_reg <= 30'h0;
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addr_reg <= 32'h0;
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data_in_reg <= 32'h0;
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data_in_reg <= 32'h0;
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wr_reg <= 1'b0;
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wr_reg <= 1'b0;
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end
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end
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else
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else
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if(strobe_i && rdy_o) begin
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if(strobe_i && rdy_o) begin
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sel_reg <= be_dec;
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sel_reg <= be_dec;
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addr_reg <= addr_i[31:2];
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addr_reg <= addr_i;
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if(!rd_wrn_i) data_in_reg <= swapped_data_i;
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if(!rd_wrn_i) data_in_reg <= swapped_data_i;
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wr_reg <= ~rd_wrn_i;
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wr_reg <= ~rd_wrn_i;
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end
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end
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end
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end
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| Line 283... |
Line 286... |
//////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////
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// Direct assignments, unsynchronized
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// Direct assignments, unsynchronized
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assign wb_dat_o = data_in_reg;
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assign wb_dat_o = data_in_reg;
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assign wb_we_o = wr_reg;
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assign wb_we_o = wr_reg;
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assign wb_adr_o = {addr_reg, 2'h0};
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assign wb_adr_o = addr_reg;
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assign wb_sel_o = sel_reg;
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assign wb_sel_o = sel_reg;
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assign data_o = data_out_reg;
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assign data_o = data_out_reg;
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assign err_o = err_reg;
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assign err_o = err_reg;
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