Line 45... |
Line 45... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: altera_virtual_jtag.vhd,v $
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// $Log: altera_virtual_jtag.vhd,v $
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// Revision 1.3 2009/06/16 02:53:19 Nathan
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// Changed some signal names for better consistency between different hardware modules.
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//
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// Revision 1.2 2009/05/17 20:54:47 Nathan
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// Revision 1.2 2009/05/17 20:54:47 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.1 2008/07/18 20:09:31 Nathan
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// Revision 1.1 2008/07/18 20:09:31 Nathan
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// Changed directory structure to match existing projects.
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// Changed directory structure to match existing projects.
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Line 69... |
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ENTITY altera_virtual_jtag IS
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ENTITY altera_virtual_jtag IS
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PORT
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PORT
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(
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(
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tck_o : OUT STD_LOGIC;
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tck_o : OUT STD_LOGIC;
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debug_tdi_i : IN STD_LOGIC;
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debug_tdo_o : IN STD_LOGIC;
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tdo_o : OUT STD_LOGIC;
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tdi_o : OUT STD_LOGIC;
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test_logic_reset_o : OUT STD_LOGIC;
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test_logic_reset_o : OUT STD_LOGIC;
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run_test_idle_o : OUT STD_LOGIC;
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run_test_idle_o : OUT STD_LOGIC;
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shift_dr_o : OUT STD_LOGIC;
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shift_dr_o : OUT STD_LOGIC;
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capture_dr_o : OUT STD_LOGIC;
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capture_dr_o : OUT STD_LOGIC;
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pause_dr_o : OUT STD_LOGIC;
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pause_dr_o : OUT STD_LOGIC;
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Line 149... |
Line 152... |
sld_sim_total_length => 0,
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sld_sim_total_length => 0,
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lpm_type => "sld_virtual_jtag"
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lpm_type => "sld_virtual_jtag"
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)
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)
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PORT MAP (
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PORT MAP (
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ir_out => ir_value,
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ir_out => ir_value,
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tdo => debug_tdi_i,
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tdo => debug_tdo_o,
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tdi => tdo_o,
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tdi => tdi_o,
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jtag_state_rti => run_test_idle_o,
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jtag_state_rti => run_test_idle_o,
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tck => tck_o,
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tck => tck_o,
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ir_in => ir_value,
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ir_in => ir_value,
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jtag_state_tlr => test_logic_reset_o,
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jtag_state_tlr => test_logic_reset_o,
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virtual_state_cir => capture_ir,
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virtual_state_cir => capture_ir,
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