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[/] [adv_debug_sys/] [trunk/] [Hardware/] [altera_virtual_jtag/] [rtl/] [vhdl/] [altera_virtual_jtag.vhd] - Diff between revs 8 and 14

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Rev 8 Rev 14
Line 45... Line 45...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: altera_virtual_jtag.vhd,v $
// $Log: altera_virtual_jtag.vhd,v $
 
// Revision 1.3  2009/06/16 02:53:19  Nathan
 
// Changed some signal names for better consistency between different hardware modules.
 
//
// Revision 1.2  2009/05/17 20:54:47  Nathan
// Revision 1.2  2009/05/17 20:54:47  Nathan
// Changed email address to opencores.org
// Changed email address to opencores.org
//
//
// Revision 1.1  2008/07/18 20:09:31  Nathan
// Revision 1.1  2008/07/18 20:09:31  Nathan
// Changed directory structure to match existing projects.
// Changed directory structure to match existing projects.
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ENTITY altera_virtual_jtag IS
ENTITY altera_virtual_jtag IS
        PORT
        PORT
        (
        (
                tck_o              : OUT STD_LOGIC;
                tck_o              : OUT STD_LOGIC;
                debug_tdi_i        :  IN STD_LOGIC;
                debug_tdo_o        :  IN STD_LOGIC;
                tdo_o              : OUT STD_LOGIC;
                tdi_o              : OUT STD_LOGIC;
                test_logic_reset_o : OUT STD_LOGIC;
                test_logic_reset_o : OUT STD_LOGIC;
                run_test_idle_o    : OUT STD_LOGIC;
                run_test_idle_o    : OUT STD_LOGIC;
                shift_dr_o         : OUT STD_LOGIC;
                shift_dr_o         : OUT STD_LOGIC;
                capture_dr_o       : OUT STD_LOGIC;
                capture_dr_o       : OUT STD_LOGIC;
                pause_dr_o         : OUT STD_LOGIC;
                pause_dr_o         : OUT STD_LOGIC;
Line 149... Line 152...
                sld_sim_total_length => 0,
                sld_sim_total_length => 0,
                lpm_type => "sld_virtual_jtag"
                lpm_type => "sld_virtual_jtag"
        )
        )
        PORT MAP (
        PORT MAP (
                ir_out => ir_value,
                ir_out => ir_value,
                tdo => debug_tdi_i,
                tdo => debug_tdo_o,
                tdi => tdo_o,
                tdi => tdi_o,
                jtag_state_rti => run_test_idle_o,
                jtag_state_rti => run_test_idle_o,
                tck => tck_o,
                tck => tck_o,
                ir_in => ir_value,
                ir_in => ir_value,
                jtag_state_tlr => test_logic_reset_o,
                jtag_state_tlr => test_logic_reset_o,
                virtual_state_cir => capture_ir,
                virtual_state_cir => capture_ir,

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