| Line 41... |
Line 41... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: tap_top.v,v $
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// $Log: tap_top.v,v $
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// Revision 1.5 2009/06/16 02:53:58 Nathan
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// Changed some signal names for better consistency between different hardware modules. Removed stale CVS log/comments.
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//
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Revision 1.4 2009/05/17 20:54:38 Nathan
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// Changed email address to opencores.org
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// Changed email address to opencores.org
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//
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//
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// Revision 1.3 2008/06/18 18:45:07 Nathan
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// Revision 1.3 2008/06/18 18:45:07 Nathan
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// Improved reset slightly. Cleanup.
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// Improved reset slightly. Cleanup.
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| Line 57... |
Line 60... |
// done in Test Logic Reset mode. Added test_logic_reset_o and
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// done in Test Logic Reset mode. Added test_logic_reset_o and
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// run_test_idle_o signals. Removed double registers from IR data
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// run_test_idle_o signals. Removed double registers from IR data
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// path. Unified the registers at the output of each data register
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// path. Unified the registers at the output of each data register
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// to a single shared FF.
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// to a single shared FF.
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//
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//
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// Revision 1.6 2004/01/27 10:00:33 mohor
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// Unused registers removed.
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//
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// Revision 1.5 2004/01/18 09:27:39 simons
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// Blocking non blocking assignmenst fixed.
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//
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// Revision 1.4 2004/01/17 17:37:44 mohor
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// capture_dr_o added to ports.
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//
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// Revision 1.3 2004/01/14 13:50:56 mohor
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// 5 consecutive TMS=1 causes reset of TAP.
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//
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// Revision 1.2 2004/01/08 10:29:44 mohor
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// Control signals for tdo_pad_o mux are changed to negedge.
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//
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// Revision 1.1 2003/12/23 14:52:14 mohor
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// Directory structure changed. New version of TAP.
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//
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// Revision 1.10 2003/10/23 18:08:01 mohor
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// MBIST chain connection fixed.
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//
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// Revision 1.9 2003/10/23 16:17:02 mohor
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// CRC logic changed.
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//
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// Revision 1.8 2003/10/21 09:48:31 simons
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// Mbist support added.
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//
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// Revision 1.7 2002/11/06 14:30:10 mohor
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// Trst active high. Inverted on higher layer.
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//
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// Revision 1.6 2002/04/22 12:55:56 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal is active high.
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//
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// Revision 1.5 2002/03/26 14:23:38 mohor
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// Signal tdo_padoe_o changed back to tdo_padoen_o.
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//
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// Revision 1.4 2002/03/25 13:16:15 mohor
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// tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
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// not named correctly.
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//
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// Revision 1.3 2002/03/12 14:30:05 mohor
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// Few outputs for boundary scan chain added.
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//
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// Revision 1.2 2002/03/12 10:31:53 mohor
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// tap_top and dbg_top modules are put into two separate modules. tap_top
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// contains only tap state machine and related logic. dbg_top contains all
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// logic necessery for debugging.
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//
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// Revision 1.1 2002/03/08 15:28:16 mohor
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// Structure changed. Hooks for jtag chain added.
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//
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//
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//
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//
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`include "tap_defines.v"
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`include "tap_defines.v"
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// Top module
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// Top module
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module tap_top(
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module tap_top(
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| Line 139... |
Line 88... |
sample_preload_select_o,
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sample_preload_select_o,
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mbist_select_o,
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mbist_select_o,
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debug_select_o,
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debug_select_o,
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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tdo_o,
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tdi_o,
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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debug_tdi_i, // from debug module
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debug_tdo_i, // from debug module
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bs_chain_tdi_i, // from Boundary Scan Chain
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bs_chain_tdo_i, // from Boundary Scan Chain
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mbist_tdi_i // from Mbist Chain
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mbist_tdo_i // from Mbist Chain
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);
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);
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// JTAG pins
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// JTAG pins
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input tms_pad_i; // JTAG test mode select pad
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input tms_pad_i; // JTAG test mode select pad
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| Line 171... |
Line 120... |
output sample_preload_select_o;
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output sample_preload_select_o;
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output mbist_select_o;
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output mbist_select_o;
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output debug_select_o;
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output debug_select_o;
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// TDO signal that is connected to TDI of sub-modules.
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// TDO signal that is connected to TDI of sub-modules.
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output tdo_o;
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output tdi_o;
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// TDI signals from sub-modules
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// TDI signals from sub-modules
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input debug_tdi_i; // from debug module
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input debug_tdo_i; // from debug module
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input bs_chain_tdi_i; // from Boundary Scan Chain
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input bs_chain_tdo_i; // from Boundary Scan Chain
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input mbist_tdi_i; // from Mbist Chain
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input mbist_tdo_i; // from Mbist Chain
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// Wires which depend on the state of the TAP FSM
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// Wires which depend on the state of the TAP FSM
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reg test_logic_reset;
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reg test_logic_reset;
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reg run_test_idle;
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reg run_test_idle;
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reg select_dr_scan;
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reg select_dr_scan;
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| Line 208... |
Line 157... |
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// TDO and enable
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// TDO and enable
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reg tdo_pad_o;
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reg tdo_pad_o;
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reg tdo_padoe_o;
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reg tdo_padoe_o;
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assign tdo_o = tdi_pad_i;
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assign tdi_o = tdi_pad_i;
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assign test_logic_reset_o = test_logic_reset;
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assign test_logic_reset_o = test_logic_reset;
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assign run_test_idle_o = run_test_idle;
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assign run_test_idle_o = run_test_idle;
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assign shift_dr_o = shift_dr;
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assign shift_dr_o = shift_dr;
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assign pause_dr_o = pause_dr;
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assign pause_dr_o = pause_dr;
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| Line 535... |
Line 484... |
* *
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* *
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**********************************************************************************/
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**********************************************************************************/
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reg tdo_mux_out; // really just a wire
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reg tdo_mux_out; // really just a wire
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always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
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always @ (shift_ir or instruction_tdo or latched_jtag_ir or idcode_tdo or
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debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or bypassed_tdo or
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debug_tdo_i or bs_chain_tdo_i or mbist_tdo_i or bypassed_tdo or
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bs_chain_tdi_i)
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bs_chain_tdo_i)
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begin
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begin
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if(shift_ir)
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if(shift_ir)
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tdo_mux_out = instruction_tdo;
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tdo_mux_out = instruction_tdo;
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else
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else
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begin
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begin
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case(latched_jtag_ir) // synthesis parallel_case
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case(latched_jtag_ir) // synthesis parallel_case
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`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
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`IDCODE: tdo_mux_out = idcode_tdo; // Reading ID code
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`DEBUG: tdo_mux_out = debug_tdi_i; // Debug
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`DEBUG: tdo_mux_out = debug_tdo_i; // Debug
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`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdi_i; // Sampling/Preloading
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`SAMPLE_PRELOAD: tdo_mux_out = bs_chain_tdo_i; // Sampling/Preloading
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`EXTEST: tdo_mux_out = bs_chain_tdi_i; // External test
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`EXTEST: tdo_mux_out = bs_chain_tdo_i; // External test
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`MBIST: tdo_mux_out = mbist_tdi_i; // Mbist test
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`MBIST: tdo_mux_out = mbist_tdo_i; // Mbist test
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default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
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default: tdo_mux_out = bypassed_tdo; // BYPASS instruction
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endcase
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endcase
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end
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end
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end
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end
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