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////////////////////////////////////////////////////////////////
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//
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// targetDebugRegisterSet.java
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//
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// Copyright (C) 2010 Nathan Yawn
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// (nyawn@opencores.org)
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//
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// This class holds a direct, cached copy of the debug registers
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// This class holds a direct, cached copy of the debug registers
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// on the OR1000 target CPU. It relies on other classes to
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// on the OR1000 target CPU. It relies on other classes to
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// interpret the meanings of the values.
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// interpret the meanings of the values.
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//
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////////////////////////////////////////////////////////////////
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU General
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// Public License as published by the Free Software Foundation;
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// either version 3.0 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU General
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// Public License along with this source; if not, download it
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// from http://www.gnu.org/licenses/gpl.html
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//
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////////////////////////////////////////////////////////////////
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package advancedWatchpointControl;
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package advancedWatchpointControl;
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public class targetDebugRegisterSet {
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public class targetDebugRegisterSet {
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public enum regType { DCR0, DVR0, DCR1, DVR1, DCR2, DVR2, DCR3, DVR3,
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public enum regType { DCR0, DVR0, DCR1, DVR1, DCR2, DVR2, DCR3, DVR3,
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