| Line 24... |
Line 24... |
*/
|
*/
|
|
|
|
|
#include <stdio.h>
|
#include <stdio.h>
|
#include <stdlib.h> // for exit()
|
#include <stdlib.h> // for exit()
|
|
#include <stdint.h>
|
|
|
#include "or32_selftest.h"
|
#include "or32_selftest.h"
|
#include "dbg_api.h"
|
#include "dbg_api.h"
|
#include "errcodes.h"
|
#include "errcodes.h"
|
|
|
| Line 143... |
Line 144... |
}
|
}
|
|
|
|
|
void init_mc(void)
|
void init_mc(void)
|
{
|
{
|
unsigned long insn;
|
uint32_t insn;
|
|
|
printf("Initialize Memory Controller (SDRAM)\n");
|
printf("Initialize Memory Controller (SDRAM)\n");
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
|
| Line 177... |
Line 178... |
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
|
CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
|
|
|
CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
|
CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
|
printf("expected %x, read %lx\n", 0xc0bf0005, insn);
|
printf("expected %x, read %x\n", 0xc0bf0005, insn);
|
}
|
}
|
|
|
|
|
void init_sram(void)
|
void init_sram(void)
|
{
|
{
|
| Line 194... |
Line 195... |
|
|
|
|
|
|
int test_sdram(void)
|
int test_sdram(void)
|
{
|
{
|
unsigned long insn;
|
uint32_t insn;
|
unsigned long i;
|
unsigned long i;
|
unsigned long data4_out[0x08];
|
uint32_t data4_out[0x08];
|
unsigned long data4_in[0x08];
|
uint32_t data4_in[0x08];
|
unsigned short data2_out[0x10];
|
uint16_t data2_out[0x10];
|
unsigned short data2_in[0x10];
|
uint16_t data2_in[0x10];
|
unsigned char data1_out[0x20];
|
uint8_t data1_out[0x20];
|
unsigned char data1_in[0x20];
|
uint8_t data1_in[0x20];
|
|
|
printf("Start SDRAM WR\n");
|
printf("Start SDRAM WR\n");
|
for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
|
for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
|
//printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
|
//printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
|
CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
|
CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
|
| Line 234... |
Line 235... |
printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
|
printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
|
CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
|
CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
|
for (i=0; i<(0x20/4); i++) {
|
for (i=0; i<(0x20/4); i++) {
|
//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
|
//printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
|
if (data4_in[i] != data4_out[i]) {
|
if (data4_in[i] != data4_out[i]) {
|
printf("SDRAM data differs. Expected: 0x%0lx, read: 0x%0lx\n", data4_in[i], data4_out[i]);
|
printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data4_in[i], data4_out[i]);
|
return APP_ERR_TEST_FAIL;
|
return APP_ERR_TEST_FAIL;
|
}
|
}
|
}
|
}
|
|
|
|
|
| Line 283... |
Line 284... |
}
|
}
|
|
|
|
|
int test_sdram_2(void)
|
int test_sdram_2(void)
|
{
|
{
|
unsigned long insn;
|
uint32_t insn;
|
|
|
printf("SDRAM test 2: \n");
|
printf("SDRAM test 2: \n");
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
|
printf("expected %x, read %lx\n", 0x12345678, insn);
|
printf("expected %x, read %x\n", 0x12345678, insn);
|
if (insn != 0x12345678) return APP_ERR_TEST_FAIL;
|
if (insn != 0x12345678) return APP_ERR_TEST_FAIL;
|
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
|
printf("expected %x, read %lx\n", 0x11112222, insn);
|
printf("expected %x, read %x\n", 0x11112222, insn);
|
if (insn != 0x11112222) return APP_ERR_TEST_FAIL;
|
if (insn != 0x11112222) return APP_ERR_TEST_FAIL;
|
|
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
|
| Line 306... |
Line 307... |
CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
|
printf("expected %x, read %lx\n", 0x11112222, insn);
|
printf("expected %x, read %x\n", 0x11112222, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
|
printf("expected %x, read %lx\n", 0x33334444, insn);
|
printf("expected %x, read %x\n", 0x33334444, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
|
printf("expected %x, read %lx\n", 0x55556666, insn);
|
printf("expected %x, read %x\n", 0x55556666, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
|
printf("expected %x, read %lx\n", 0x77778888, insn);
|
printf("expected %x, read %x\n", 0x77778888, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
|
printf("expected %x, read %lx\n", 0x9999aaaa, insn);
|
printf("expected %x, read %x\n", 0x9999aaaa, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
|
printf("expected %x, read %lx\n", 0xbbbbcccc, insn);
|
printf("expected %x, read %x\n", 0xbbbbcccc, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
|
printf("expected %x, read %lx\n", 0xddddeeee, insn);
|
printf("expected %x, read %x\n", 0xddddeeee, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
|
printf("expected %x, read %lx\n", 0xffff0000, insn);
|
printf("expected %x, read %x\n", 0xffff0000, insn);
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
|
CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
|
printf("expected %x, read %lx\n", 0xdeadbeef, insn);
|
printf("expected %x, read %x\n", 0xdeadbeef, insn);
|
|
|
if (insn != 0xdeadbeef) {
|
if (insn != 0xdeadbeef) {
|
printf("SDRAM test 2 FAILED\n");
|
printf("SDRAM test 2 FAILED\n");
|
return APP_ERR_TEST_FAIL;
|
return APP_ERR_TEST_FAIL;
|
}
|
}
|
| Line 338... |
Line 339... |
|
|
|
|
int test_sram(void)
|
int test_sram(void)
|
{
|
{
|
//unsigned long insn;
|
//unsigned long insn;
|
unsigned long ins;
|
uint32_t ins;
|
unsigned long insn[9];
|
uint32_t insn[9];
|
insn[0] = 0x11112222;
|
insn[0] = 0x11112222;
|
insn[1] = 0x33334444;
|
insn[1] = 0x33334444;
|
insn[2] = 0x55556666;
|
insn[2] = 0x55556666;
|
insn[3] = 0x77778888;
|
insn[3] = 0x77778888;
|
insn[4] = 0x9999aaaa;
|
insn[4] = 0x9999aaaa;
|
| Line 365... |
Line 366... |
CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
|
CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
|
CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
|
|
|
|
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &ins));
|
printf("expected %x, read %lx\n", 0x11112222, ins);
|
printf("expected %x, read %x\n", 0x11112222, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &ins));
|
printf("expected %x, read %lx\n", 0x33334444, ins);
|
printf("expected %x, read %x\n", 0x33334444, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &ins));
|
printf("expected %x, read %lx\n", 0x55556666, ins);
|
printf("expected %x, read %x\n", 0x55556666, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &ins));
|
printf("expected %x, read %lx\n", 0x77778888, ins);
|
printf("expected %x, read %x\n", 0x77778888, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &ins));
|
printf("expected %x, read %lx\n", 0x9999aaaa, ins);
|
printf("expected %x, read %x\n", 0x9999aaaa, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &ins));
|
printf("expected %x, read %lx\n", 0xbbbbcccc, ins);
|
printf("expected %x, read %x\n", 0xbbbbcccc, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &ins));
|
printf("expected %x, read %lx\n", 0xddddeeee, ins);
|
printf("expected %x, read %x\n", 0xddddeeee, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &ins));
|
printf("expected %x, read %lx\n", 0xffff0000, ins);
|
printf("expected %x, read %x\n", 0xffff0000, ins);
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &ins));
|
CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &ins));
|
printf("expected %x, read %lx\n", 0xdedababa, ins);
|
printf("expected %x, read %x\n", 0xdedababa, ins);
|
|
|
if (ins != 0xdedababa) {
|
if (ins != 0xdedababa) {
|
printf("SRAM test failed!!!\n");
|
printf("SRAM test failed!!!\n");
|
return APP_ERR_TEST_FAIL;
|
return APP_ERR_TEST_FAIL;
|
}
|
}
|
| Line 397... |
Line 398... |
|
|
|
|
|
|
int test_or1k_cpu0(void)
|
int test_or1k_cpu0(void)
|
{
|
{
|
unsigned long npc, ppc, r1, insn;
|
uint32_t npc, ppc, r1, insn;
|
unsigned char stalled;
|
uint8_t stalled;
|
unsigned long result;
|
uint32_t result;
|
int i;
|
int i;
|
|
|
printf("Testing CPU0 (or1k) - writing instructions\n");
|
printf("Testing CPU0 (or1k) - writing instructions\n");
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005)); /* l.xor r0,r0,r0 */
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005)); /* l.xor r0,r0,r0 */
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000)); /* l.addi r1,r0,0x0 */
|
CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000)); /* l.addi r1,r0,0x0 */
|
| Line 431... |
Line 432... |
}
|
}
|
|
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 5);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 5);
|
result = npc + ppc + r1;
|
result = npc + ppc + r1;
|
|
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 0)); // Reset step bit
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 0)); // Reset step bit
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn)); // Set trap insn in delay slot
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn)); // Set trap insn in delay slot
|
| Line 444... |
Line 445... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn)); // Set back original insn
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn)); // Set back original insn
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 8);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 8);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn)); // Set trap insn in place of branch insn
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn)); // Set trap insn in place of branch insn
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
|
| Line 457... |
Line 458... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); // Read NPC
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); // Read PPC
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
CHECK(dbg_cpu0_read(0x401, &r1)); // Read R1
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn)); // Set back original insn
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn)); // Set back original insn
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 11);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 11);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn before branch insn */
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn before branch insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
| Line 470... |
Line 471... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 24);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 24);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn)); /* Set trap insn behind lsu insn */
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn)); /* Set trap insn behind lsu insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
|
| Line 483... |
Line 484... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn)); /* Set back original insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000020, 0x0000001c, 49);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000020, 0x0000001c, 49);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn very near previous one */
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn)); /* Set trap insn very near previous one */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
|
| Line 496... |
Line 497... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 50);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000024, 0x00000020, 50);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn)); /* Set trap insn to the start */
|
CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn)); /* Set trap insn to the start */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
|
| Line 509... |
Line 510... |
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn)); /* Set back original insn */
|
CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn)); /* Set back original insn */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000014, 0x00000010, 99);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000014, 0x00000010, 99);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22)); /* Set step bit */
|
for(i = 0; i < 5; i++) {
|
for(i = 0; i < 5; i++) {
|
| Line 523... |
Line 524... |
//printf("got trap.\n");
|
//printf("got trap.\n");
|
}
|
}
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 101);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000028, 0x00000024, 101);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
|
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24)); /* Set PC */
|
CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24)); /* Set PC */
|
for(i = 0; i < 2; i++) {
|
for(i = 0; i < 2; i++) {
|
| Line 537... |
Line 538... |
//printf("Got trap.\n");
|
//printf("Got trap.\n");
|
}
|
}
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 16, &npc)); /* Read NPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc)); /* Read PPC */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
CHECK(dbg_cpu0_read(0x401, &r1)); /* Read R1 */
|
printf("Read npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
|
printf("Read npc = %.8x ppc = %.8x r1 = %.8x\n", npc, ppc, r1);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 201);
|
printf("Expected npc = %.8x ppc = %.8x r1 = %.8x\n", 0x00000010, 0x00000028, 201);
|
result = npc + ppc + r1 + result;
|
result = npc + ppc + r1 + result;
|
printf("result = %.8lx\n", result ^ 0xdeaddae1);
|
printf("result = %.8x\n", result ^ 0xdeaddae1);
|
|
|
if((result ^ 0xdeaddae1) != 0xdeaddead)
|
if((result ^ 0xdeaddae1) != 0xdeaddead)
|
return APP_ERR_TEST_FAIL;
|
return APP_ERR_TEST_FAIL;
|
|
|
return APP_ERR_NONE;
|
return APP_ERR_NONE;
|
