| Line 36... |
Line 36... |
#include <fcntl.h>
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#include <fcntl.h>
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#include <arpa/inet.h>
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#include <arpa/inet.h>
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#include <poll.h>
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#include <poll.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp.h>
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#include <string.h>
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#include <string.h>
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#include <netinet/in.h>
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/* Package includes */
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/* Package includes */
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#include "except.h"
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#include "except.h"
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#include "spr-defs.h"
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#include "spr-defs.h"
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#include "dbg_api.h"
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#include "dbg_api.h"
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| Line 497... |
Line 498... |
if (rsp.client_waiting)
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if (rsp.client_waiting)
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{
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{
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// Read the PPC
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// Read the PPC
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dbg_cpu0_read(SPR_PPC, &ppcval);
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dbg_cpu0_read(SPR_PPC, &ppcval);
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if ((TARGET_SIGNAL_TRAP == rsp.sigval) &&
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// This is structured the way it is to avoid the read of DMR2 unless it's necessary.
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(NULL != mp_hash_lookup (BP_MEMORY, ppcval))) // We also get TRAP from a single-step, don't change npc unless it's really a BP
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if (TARGET_SIGNAL_TRAP == rsp.sigval)
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{
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{
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if(NULL != mp_hash_lookup (BP_MEMORY, ppcval)) // Is this a breakpoint we set? (we also get a TRAP on single-step)
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{
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//fprintf(stderr, "Resetting NPC to PPC\n");
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set_npc(ppcval);
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}
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else
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{
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uint32_t dmr2val;
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dbg_cpu0_read(SPR_DMR2, &dmr2val); // We need this to check for a hardware breakpoint
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if((dmr2val & SPR_DMR2_WBS) != 0) // Is this a hardware breakpoint?
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{
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//fprintf(stderr, "Resetting NPC to PPC\n");
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set_npc (ppcval);
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set_npc (ppcval);
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}
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}
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}
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}
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rsp_report_exception();
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rsp_report_exception();
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rsp.client_waiting = 0; /* No longer waiting */
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rsp.client_waiting = 0; /* No longer waiting */
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}
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}
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}
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}
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| Line 1730... |
Line 1745... |
static void
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static void
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rsp_continue_generic (unsigned long int except)
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rsp_continue_generic (unsigned long int except)
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{
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{
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uint32_t tmp;
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uint32_t tmp;
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/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
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/* Clear Debug Reason Register */
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Register 2 */
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dbg_cpu0_write(SPR_DRR, 0);
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dbg_cpu0_write(SPR_DRR, 0);
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/* Clear any watchpoints indicated in DMR2. Any write to DMR2 will clear this (undocumented feature). */
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dbg_cpu0_read(SPR_DMR2, &tmp);
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dbg_cpu0_read(SPR_DMR2, &tmp);
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tmp &= ~SPR_DMR2_WGB;
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if(tmp & SPR_DMR2_WBS) { // don't waste the time writing if no hw breakpoints set
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dbg_cpu0_write(SPR_DMR2, tmp);
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dbg_cpu0_write(SPR_DMR2, tmp);
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}
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/* Clear the single step trigger in Debug Mode Register 1 and set traps to be
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/* Clear the single step trigger in Debug Mode Register 1 and set traps to be
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handled by the debug unit in the Debug Stop Register */
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handled by the debug unit in the Debug Stop Register */
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dbg_cpu0_read(SPR_DMR1, &tmp);
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dbg_cpu0_read(SPR_DMR1, &tmp);
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tmp &= ~(SPR_DMR1_ST|SPR_DMR1_BT); // clear single-step and trap-on-branch
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tmp &= ~(SPR_DMR1_ST|SPR_DMR1_BT); // clear single-step and trap-on-branch
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| Line 2445... |
Line 2462... |
static void
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static void
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rsp_step_generic (unsigned long int except)
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rsp_step_generic (unsigned long int except)
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{
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{
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uint32_t tmp;
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uint32_t tmp;
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/* Clear Debug Reason Register and watchpoint break generation in Debug Mode
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/* Clear Debug Reason Register */
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Register 2 */
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tmp = 0;
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tmp = 0;
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dbg_cpu0_write(SPR_DRR, tmp); // *** TODO Check return value of all hardware accesses
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dbg_cpu0_write(SPR_DRR, tmp); // *** TODO Check return value of all hardware accesses
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/* Clear any watchpoint indicators in DMR2. Any write to DMR2 will do this (undocumented feature) */
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dbg_cpu0_read(SPR_DMR2, &tmp);
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dbg_cpu0_read(SPR_DMR2, &tmp);
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if(tmp & SPR_DMR2_WGB) {
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if(tmp & SPR_DMR2_WBS) { // If no HW breakpoints, don't waste time writing
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tmp &= ~SPR_DMR2_WGB;
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dbg_cpu0_write(SPR_DMR2, tmp);
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dbg_cpu0_write(SPR_DMR2, tmp);
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}
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}
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/* Set the single step trigger in Debug Mode Register 1 and set traps to be
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/* Set the single step trigger in Debug Mode Register 1 and set traps to be
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handled by the debug unit in the Debug Stop Register */
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handled by the debug unit in the Debug Stop Register */
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