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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_ctrl.v] - Diff between revs 191 and 204

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Rev 191 Rev 204
Line 86... Line 86...
   reg [4:0]             ra_of;
   reg [4:0]             ra_of;
   reg [4:0]             rd_ex;
   reg [4:0]             rd_ex;
   reg [4:0]             rd_of;
   reg [4:0]             rd_of;
   // End of automatics
   // End of automatics
 
 
   wire                 fINT;
   wire                 fINT, fXCE;
   //wire [31:0]                wXCEOP = 32'hBA2D0020; // Vector 0x20
   wire [31:0]           wXCEOP = 32'hBA2E0020; // Vector 0x20
   wire [31:0]           wINTOP = 32'hB9CD0010; // Vector 0x10   
   wire [31:0]           wINTOP = 32'hB9CD0010; // Vector 0x10   
   //wire [31:0]                wNOPOP = 32'h88000000; // branch-no-delay/stall
   //wire [31:0]                wNOPOP = 32'h88000000; // branch-no-delay/stall
 
 
   wire [1:0]            mux_opa, mux_opb, mux_opd;
   wire [1:0]            mux_opa, mux_opb, mux_opd;
 
 
Line 99... Line 99...
   wire [4:0]            wRD, wRA, wRB;
   wire [4:0]            wRD, wRA, wRB;
   wire [5:0]            wOPC;
   wire [5:0]            wOPC;
   wire [15:0]           wIMM;
   wire [15:0]           wIMM;
   wire [31:0]           imm_if;
   wire [31:0]           imm_if;
 
 
   assign               {wOPC, wRD, wRA, wIMM} = (fINT) ? wINTOP : ich_dat;
   assign               {wOPC, wRD, wRA, wIMM} = (fXCE) ? wXCEOP :
 
                                                 (fINT) ? wINTOP :
 
                                                 ich_dat;
   assign               wRB = wIMM[15:11];
   assign               wRB = wIMM[15:11];
 
 
   // decode main opgroups
   // decode main opgroups
 
 
   //wire               fSFT = (wOPC == 6'o44);
   //wire               fSFT = (wOPC == 6'o44);
Line 192... Line 194...
        rIMM1 <= #1 rIMM0;
        rIMM1 <= #1 rIMM0;
        rIMM0 <= #1 wIMM;
        rIMM0 <= #1 wIMM;
     end
     end
 
 
   assign fINT = brk_if[0] & gpha & !rFIM1;
   assign fINT = brk_if[0] & gpha & !rFIM1;
 
   assign fXCE = brk_if[1] & !rFIM1;
 
 
   // operand latch   
   // operand latch   
   reg                  wrb_ex;
   reg                  wrb_ex;
   reg                  fwd_ex;
   reg                  fwd_ex;
   reg [2:0]             mux_mx;
   reg [2:0]             mux_mx;
Line 278... Line 281...
                                  //(wFMUL | wFBSF | wFMEM | wFMOV);
                                  //(wFMUL | wFBSF | wFMEM | wFMOV);
   assign               hzd_bpc = (bra_ex[1] & !bra_ex[0]);
   assign               hzd_bpc = (bra_ex[1] & !bra_ex[0]);
 
 
endmodule // aeMB2_ctrl
endmodule // aeMB2_ctrl
 
 
/*
 
 $Log: not supported by cvs2svn $
 
 Revision 1.6  2008/05/01 08:32:58  sybreon
 
 Added interrupt capability.
 
 
 
 Revision 1.5  2008/04/28 08:15:25  sybreon
 
 Optimisations.
 
 
 
 Revision 1.4  2008/04/26 17:57:43  sybreon
 
 Minor performance improvements.
 
 
 
 Revision 1.3  2008/04/26 01:09:05  sybreon
 
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 
 
 Revision 1.2  2008/04/20 16:34:32  sybreon
 
 Basic version with some features left out.
 
 
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 
 Initial import.
 
*/
 
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