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*/
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*/
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module aeMB2_dwbif (/*AUTOARG*/
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module aeMB2_dwbif (/*AUTOARG*/
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// Outputs
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// Outputs
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_adr_o, dwb_sel_o, dwb_stb_o, dwb_cyc_o, dwb_tag_o, dwb_wre_o,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx,
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dwb_dat_o, dwb_fb, sel_mx, dwb_mx, exc_dwb,
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// Inputs
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// Inputs
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dwb_dat_i, dwb_ack_i, imm_of, opd_of, opc_of, opa_of, opb_of,
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dwb_dat_i, dwb_ack_i, dwb_err_i, imm_of, opd_of, opc_of, opa_of,
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msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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opb_of, msr_ex, mem_ex, sfr_mx, gclk, grst, dena, gpha
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);
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);
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parameter AEMB_DWB = 32; ///< data bus address width
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parameter AEMB_DWB = 32; ///< data bus address width
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// DWB control signals
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// DWB control signals
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output [AEMB_DWB-1:2] dwb_adr_o;
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output [AEMB_DWB-1:2] dwb_adr_o;
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dwb_tag_o, // cache enable
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dwb_tag_o, // cache enable
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dwb_wre_o;
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dwb_wre_o;
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output [31:0] dwb_dat_o;
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output [31:0] dwb_dat_o;
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input [31:0] dwb_dat_i;
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input [31:0] dwb_dat_i;
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input dwb_ack_i;
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input dwb_ack_i;
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input dwb_err_i; // for bus error exception
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// INTERNAL
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// INTERNAL
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output dwb_fb;
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output dwb_fb;
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output [3:0] sel_mx;
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output [3:0] sel_mx;
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output [31:0] dwb_mx;
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output [31:0] dwb_mx;
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input [1:0] opb_of;
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input [1:0] opb_of;
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input [7:0] msr_ex;
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input [7:0] msr_ex;
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input [AEMB_DWB-1:2] mem_ex;
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input [AEMB_DWB-1:2] mem_ex;
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input [7:5] sfr_mx;
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input [7:5] sfr_mx;
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// EXC signals
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output [1:0] exc_dwb; // 1: unaligned; 0: bus error
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// SYS signals
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// SYS signals
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input gclk,
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input gclk,
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grst,
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grst,
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dena,
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dena,
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gpha;
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gpha;
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/*AUTOREG*/
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg dwb_cyc_o;
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reg [31:0] dwb_dat_o;
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reg [31:0] dwb_mx;
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reg [3:0] dwb_sel_o;
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reg [3:0] dwb_sel_o;
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reg dwb_stb_o;
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reg dwb_stb_o, dwb_cyc_o, dwb_wre_o;
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reg dwb_wre_o;
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reg [31:0] dwb_dat_o;
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reg [3:0] sel_mx;
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reg [3:0] sel_mx;
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// End of automatics
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reg [31:0] dwb_mx;
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reg dwb_exc;
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [1:0] wOFF = (opa_of[1:0] + opb_of[1:0]); // small adder
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wire [3:0] wSEL = {opc_of[1:0], wOFF};
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wire [3:0] wSEL = {opc_of[1:0], wOFF}; // byte selector info
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// ENABLE FEEDBACK
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i);
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// DATA bus
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assign dwb_fb = (dwb_stb_o ~^ dwb_ack_i); // feedback
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assign dwb_adr_o = mem_ex; // passthru
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assign dwb_adr_o = mem_ex; // data-bus passthru
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assign exc_dwb = {dwb_exc, dwb_err_i}; // exception signal
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// STORE SIZER
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// STORE SIZER
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// TODO: Move the right words to the right place
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// TODO: Move the right words to the right place
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// TODO: Make this work with dwb_mx to for partial word loads.
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// TODO: Make this work with dwb_mx to for partial word loads.
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// WISHBONE PIPELINE
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// WISHBONE PIPELINE
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_exc <= 1'h0;
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dwb_mx <= 32'h0;
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dwb_mx <= 32'h0;
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dwb_sel_o <= 4'h0;
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dwb_sel_o <= 4'h0;
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dwb_wre_o <= 1'h0;
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dwb_wre_o <= 1'h0;
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sel_mx <= 4'h0;
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sel_mx <= 4'h0;
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// End of automatics
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// End of automatics
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4'hC, 4'hD, 4'hE, 4'hF:
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4'hC, 4'hD, 4'hE, 4'hF:
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dwb_sel_o <= #1 4'h0;
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dwb_sel_o <= #1 4'h0;
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// TODO: ILLEGAL
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// TODO: ILLEGAL
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default: dwb_sel_o <= #1 4'hX;
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default: dwb_sel_o <= #1 4'hX;
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endcase // case (wSEL)
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endcase // case (wSEL)
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// exception checking
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case (opc_of[1:0])
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2'o2: dwb_exc <= #1 |wOFF[1:0];
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2'o1: dwb_exc <= #1 wOFF[0];
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default: dwb_exc <= #1 1'b0;
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endcase // case (opc_of[1:0])
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end // if (dena)
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end // if (dena)
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// Independent on pipeline
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// Independent of pipeline
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always @(posedge gclk)
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always @(posedge gclk)
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if (grst) begin
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if (grst) begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_lat <= 32'h0;
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dwb_lat <= 32'h0;
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// End of automatics
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// End of automatics
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end else if (dwb_ack_i) begin
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end else if (dwb_ack_i) begin // if (grst)
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// LATCH READS
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// LATCH READS
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dwb_lat <= #1 dwb_dat_i;
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dwb_lat <= #1 dwb_dat_i;
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end
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end
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always @(posedge gclk)
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always @(posedge gclk)
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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dwb_cyc_o <= 1'h0;
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dwb_cyc_o <= 1'h0;
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dwb_stb_o <= 1'h0;
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dwb_stb_o <= 1'h0;
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// End of automatics
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// End of automatics
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//end else if (dwb_fb) begin
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//end else if (dwb_fb) begin
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end else if (dwb_fb) begin
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end else if (dwb_fb) begin // if (grst)
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dwb_stb_o <= #1
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dwb_stb_o <= #1
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(dena) ? &opc_of[5:4] : // LXX/SSS
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(dena) ? &opc_of[5:4] : // LXX/SSS
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(dwb_stb_o & !dwb_ack_i); // LXX/SSS
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(dwb_stb_o & !dwb_ack_i); // LXX/SSS
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dwb_cyc_o <= #1
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dwb_cyc_o <= #1
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(dena) ? &opc_of[5:4] | msr_ex[0] :
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(dena) ? &opc_of[5:4] | msr_ex[0] :
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(dwb_stb_o & !dwb_ack_i) | msr_ex[0];
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(dwb_stb_o & !dwb_ack_i) | msr_ex[0];
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end
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end
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assign dwb_tag_o = msr_ex[7]; // MSR_DCE
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assign dwb_tag_o = msr_ex[7]; // MSR_DCE
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endmodule // aeMB2_dwbif
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endmodule // unmatched end(function|task|module|primitive|interface|package|class|clocking)
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/*
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$Log: not supported by cvs2svn $
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Revision 1.6 2008/04/26 17:57:43 sybreon
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Minor performance improvements.
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Revision 1.5 2008/04/26 01:09:05 sybreon
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Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
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Revision 1.4 2008/04/23 14:18:52 sybreon
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Fixed pipelined latching of data bug.
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Revision 1.3 2008/04/21 12:11:38 sybreon
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Passes arithmetic tests with single thread.
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Revision 1.2 2008/04/20 16:34:32 sybreon
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Basic version with some features left out.
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Revision 1.1 2008/04/18 00:21:52 sybreon
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Initial import.
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*/
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No newline at end of file
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No newline at end of file
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