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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB2_intu.v] - Diff between revs 191 and 204

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Rev 191 Rev 204
Line 50... Line 50... 
   input [31:0]  opb_of;
 
   input [31:0]  opb_of;
 
   input [31:0]  opd_of;
 
   input [31:0]  opd_of;
 
   input [15:0]  imm_of;
 
   input [15:0]  imm_of;
 
   input [4:0]    rd_of,
 
   input [4:0]    rd_of,
 
                 ra_of;
 
                 ra_of;
 
   output [7:0]  msr_ex;
 
   output [9:0]  msr_ex;
 
   output [31:0] sfr_mx;
 
   output [31:0] sfr_mx;
 
 
 
 
 
   // SYS signals
 
   // SYS signals
 
   input         gclk,
 
   input         gclk,
 
                 grst,
 
                 grst,
Line 78... Line 78... 
                        MUX_RPC = 3'o2,
 
                        MUX_RPC = 3'o2,
 
                        MUX_ALU = 3'o1,
 
                        MUX_ALU = 3'o1,
 
                        MUX_NOP = 3'o0;
 
                        MUX_NOP = 3'o0;
 
 
 
 
 
   reg                  rMSR_C,
 
   reg                  rMSR_C,
 
 
 
                        rMSR_EE,
 
 
 
                        rMSR_EIP,
 
                        rMSR_CC,
 
                        rMSR_CC,
 
                        rMSR_MTX,
 
                        rMSR_MTX,
 
                        rMSR_DTE,
 
                        rMSR_DTE,
 
                        rMSR_ITE,
 
                        rMSR_ITE,
 
                        rMSR_BIP,
 
                        rMSR_BIP,
Line 179... Line 181... 
    1  - IE (interrupt enable)
 
    1  - IE (interrupt enable)
 
    0  - BE (bus-lock enable)
 
    0  - BE (bus-lock enable)
 
    */
 
    */
 
 
 
 
 
   assign msr_ex = {
 
   assign msr_ex = {
 
 
 
                    rMSR_EIP,
 
 
 
                    rMSR_EE,
 
                    rMSR_DTE,
 
                    rMSR_DTE,
 
                    1'b0,
 
                    1'b0,
 
                    rMSR_ITE,
 
                    rMSR_ITE,
 
                    rMSR_MTX,
 
                    rMSR_MTX,
 
                    rMSR_BIP,
 
                    rMSR_BIP,
Line 190... Line 194... 
                    rMSR_IE,
 
                    rMSR_IE,
 
                    rMSR_BE
 
                    rMSR_BE
 
                    };
 
                    };
 
 
 
 
 
   // MSRSET/MSRCLR (small ALU)
 
   // MSRSET/MSRCLR (small ALU)
 
   wire [7:0] wRES = (ra_of[0]) ?
 
   wire [9:0] wRES = (ra_of[0]) ?
 
              (msr_ex[7:0]) & ~imm_of[7:0] : // MSRCLR
 
              (msr_ex[9:0]) & ~imm_of[9:0] : // MSRCLR
 
              (msr_ex[7:0]) | imm_of[7:0]; // MSRSET      
              (msr_ex[9:0]) | imm_of[9:0]; // MSRSET      
 
 
 
 
   // 0 - Break
 
   // 0 - Break
 
   // 1 - Interrupt
 
   // 1 - Interrupt
 
   // 2 - Exception
 
   // 2 - Exception
 
   // 3 - Reserved
 
   // 3 - Reserved
 
   wire       fRTID = (opc_of == 6'o55) & rd_of[0];
 
 
 
 
 
   // break
 
   wire       fRTBD = (opc_of == 6'o55) & rd_of[1];
 
   wire       fRTBD = (opc_of == 6'o55) & rd_of[1];
 
 
 
   wire       fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
 
 
 
 
 
 
 
   // interrupt
 
 
 
   wire       fRTID = (opc_of == 6'o55) & rd_of[0];
 
   wire       fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
 
   wire       fBRKI = (opc_of == 6'o56) & (ra_of[4:0] == 5'hD);
 
   wire       fBRKB = ((opc_of == 6'o46) | (opc_of == 6'o56)) & (ra_of[4:0] == 5'hC);
 
 
 
 
 
   // exception
 
 
 
   wire       fRTED = (opc_of == 6'o55) & rd_of[2];
 
 
 
   wire       fBRKE = (opc_of == 6'o56) & (ra_of[4:0] == 5'hE);
 
 
 
 
 
   wire       fMOV = (opc_of == 6'o45);
 
   wire       fMOV = (opc_of == 6'o45);
 
   wire       fMTS = fMOV & &imm_of[15:14];
 
   wire       fMTS = fMOV & &imm_of[15:14];
 
   wire       fMOP = fMOV & ~|imm_of[15:14];
 
   wire       fMOP = fMOV & ~|imm_of[15:14];
 
 
 
 
Line 273... Line 284... 
                    (fBRKB) ? 1'b1 :
 
                    (fBRKB) ? 1'b1 :
 
                    (fRTBD) ? 1'b0 :
 
                    (fRTBD) ? 1'b0 :
 
                    (fMTS) ? opa_of[3] :
 
                    (fMTS) ? opa_of[3] :
 
                    (fMOP) ? wRES[3] :
 
                    (fMOP) ? wRES[3] :
 
                    rMSR_BIP;
 
                    rMSR_BIP;
 
 
 
 
 
 
 
        rMSR_EE <= #1
 
 
 
                   (fBRKE) ? 1'b0 :
 
 
 
                   (fRTED) ? 1'b1 :
 
 
 
                   (fMTS) ? opa_of[8] :
 
 
 
                   (fMOP) ? wRES[8] :
 
 
 
                   rMSR_EE;
 
 
 
 
 
 
 
        rMSR_EIP <= #1
 
 
 
                    (fBRKE) ? 1'b1 :
 
 
 
                    (fRTED) ? 1'b0 :
 
 
 
                    (fMTS) ? opa_of[9] :
 
 
 
                    (fMOP) ? wRES[9] :
 
 
 
                    rMSR_EIP;
 
 
 
 
 
        /*
 
        /*
 
 
 
 
 
        case ({fMTS, fMOP})
 
        case ({fMTS, fMOP})
 
          2'o2: {rMSR_DTE,
 
          2'o2: {rMSR_DTE,
 
                 rMSR_ITE,
 
                 rMSR_ITE,
Line 355... Line 381... 
        */
 
        */
 
     end
 
     end
 
 
 
 
 
endmodule // aeMB2_intu
 
endmodule // aeMB2_intu
 
 
 
 
 
/*
 
 
 
 $Log: not supported by cvs2svn $
 
 
 
 Revision 1.6  2008/04/28 08:15:25  sybreon
 
 
 
 Optimisations.
 
 
 
 
 
 
 
 Revision 1.5  2008/04/26 17:57:43  sybreon
 
 
 
 Minor performance improvements.
 
 
 
 
 
 
 
 Revision 1.4  2008/04/26 01:09:06  sybreon
 
 
 
 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.
 
 
 
 
 
 
 
 Revision 1.3  2008/04/23 14:18:30  sybreon
 
 
 
 Fixed CMP bug.
 
 
 
 
 
 
 
 Revision 1.2  2008/04/21 12:11:38  sybreon
 
 
 
 Passes arithmetic tests with single thread.
 
 
 
 
 
 
 
 Revision 1.1  2008/04/18 00:21:52  sybreon
 
 
 
 Initial import.
 
 
 
*/
 
 
 
 
 
 
 
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