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module aeMB2_iwbif (/*AUTOARG*/
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module aeMB2_iwbif (/*AUTOARG*/
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// Outputs
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// Outputs
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iwb_adr_o, iwb_stb_o, iwb_sel_o, iwb_wre_o, iwb_cyc_o, iwb_tag_o,
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iwb_adr_o, iwb_stb_o, iwb_sel_o, iwb_wre_o, iwb_cyc_o, iwb_tag_o,
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ich_adr, fet_fb, rpc_if, rpc_mx, exc_iwb,
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ich_adr, fet_fb, rpc_if, rpc_mx, exc_iwb,
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// Inputs
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// Inputs
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iwb_ack_i, iwb_dat_i, iwb_err_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd,
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iwb_ack_i, iwb_dat_i, ich_hit, msr_ex, hzd_bpc, hzd_fwd,
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bra_ex, bpc_ex, gclk, grst, dena, iena, gpha
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bra_ex, bpc_ex, gclk, grst, dena, iena, gpha
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);
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);
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parameter AEMB_IWB = 32;
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parameter AEMB_IWB = 32;
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parameter AEMB_HTX = 1;
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parameter AEMB_HTX = 1;
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output iwb_wre_o;
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output iwb_wre_o;
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output iwb_cyc_o;
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output iwb_cyc_o;
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output iwb_tag_o;
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output iwb_tag_o;
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input iwb_ack_i;
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input iwb_ack_i;
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input [31:0] iwb_dat_i;
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input [31:0] iwb_dat_i;
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input iwb_err_i; // bus error exception
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//input iwb_err_i; // bus error exception
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// Cache
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// Cache
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output [AEMB_IWB-1:2] ich_adr;
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output [AEMB_IWB-1:2] ich_adr;
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input ich_hit;
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input ich_hit;
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assign iwb_cyc_o = iwb_stb_o;
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assign iwb_cyc_o = iwb_stb_o;
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assign iwb_tag_o = msr_ex[5];
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assign iwb_tag_o = msr_ex[5];
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assign fet_fb = iwb_stb_o ~^ iwb_ack_i; // no WB cycle
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assign fet_fb = iwb_stb_o ~^ iwb_ack_i; // no WB cycle
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assign exc_iwb = iwb_err_i; // exception pass-thru
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// TODO: enable iwb_err_i exception pass-thru
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assign exc_iwb = 1'b0;
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endmodule // aeMB2_iwbif
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endmodule // aeMB2_iwbif
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