| Line 144... |
Line 144... |
4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
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default: begin
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default: begin
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$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
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//$displayh("\n*** INVALID WRITE ",{dwb_adr_o,2'o0}, " ***");
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//$finish;
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//$finish;
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end
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end
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
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end // if (dwb_wre_o & dwb_stb_o & dwb_ack_i)
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|
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if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
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if (dwb_stb_o & !dwb_wre_o & dwb_ack_i) begin
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case (dwb_sel_o)
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case (dwb_sel_o)
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4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
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4'h1,4'h2,4'h4,4'h8,4'h3,4'hC,4'hF: begin
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end
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end
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default: begin
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default: begin
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$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
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//$displayh("\n*** INVALID READ ",{dwb_adr_o,2'd0}, " ***");
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//$finish;
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//$finish;
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end
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end
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endcase // case (dwb_sel_o)
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endcase // case (dwb_sel_o)
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end
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end
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