| Line 43... |
Line 43... |
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`timescale 1 ns/1 ps
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`timescale 1 ns/1 ps
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module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out,aes_en);
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module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out);
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input clk, rst;
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input clk, rst;
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input ld;
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input ld;
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output done;
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output done;
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input [127:0] key;
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input [127:0] key;
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input [127:0] text_in;
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input [127:0] text_in;
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output [127:0] text_out;
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output [127:0] text_out;
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input aes_en;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires
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// Local Wires
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//
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//
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| Line 125... |
Line 125... |
//
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//
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// Misc Logic
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// Misc Logic
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(aes_en)
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begin
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begin
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if(rst) begin dcnt <= 4'h0; end
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if(~rst) begin dcnt <= 4'h0; end
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else
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else
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if(ld) begin dcnt <= 4'h6; end
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if(ld) begin dcnt <= 4'h6; end
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else
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else
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if(|dcnt) begin dcnt <= dcnt - 4'h1; end
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if(|dcnt) begin dcnt <= dcnt - 4'h1; end
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Line 281... |
assign sa32_next_round2 = sa32_mc ^ w6[07:00];
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assign sa32_next_round2 = sa32_mc ^ w6[07:00];
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assign sa33_next_round2 = sa33_mc ^ w7[07:00];
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assign sa33_next_round2 = sa33_mc ^ w7[07:00];
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always @(posedge clk)
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always @(posedge clk)
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if(aes_en && ~rst)
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begin
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begin
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/* $strobe($time,": roundkeyodd = %h, text_out_odd is %h\n",{w0,w1,w2,w3},text_out_temp);
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/* $strobe($time,": roundkeyodd = %h, text_out_odd is %h\n",{w0,w1,w2,w3},text_out_temp);
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$strobe($time,": roundkeyeven is %h\n",{w4,w5,w6,w7}); */
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$strobe($time,": roundkeyeven is %h\n",{w4,w5,w6,w7}); */
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text_out_temp[127:120] <= sa00_sr ^ w4[31:24];
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text_out_temp[127:120] <= sa00_sr ^ w4[31:24];
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Line 362... |
// Final text output
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// Final text output
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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if(aes_en && ~rst)
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begin
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begin
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/* $strobe($time,": round_key2 is %h\n",{w4,w5,w6,w7});
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/* $strobe($time,": round_key2 is %h\n",{w4,w5,w6,w7});
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$strobe($time,": roundkeyeven = %h, text_out_even is %h\n",{w4,w5,w6,w7},text_out);*/
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$strobe($time,": roundkeyeven = %h, text_out_even is %h\n",{w4,w5,w6,w7},text_out);*/
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text_out[127:120] <= sa00_sr_round2 ^ w0[31:24];
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text_out[127:120] <= sa00_sr_round2 ^ w0[31:24];
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text_out[095:088] <= sa01_sr_round2 ^ w1[31:24];
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text_out[095:088] <= sa01_sr_round2 ^ w1[31:24];
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Line 384... |
text_out[039:032] <= sa32_sr_round2 ^ w2[07:00];
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text_out[039:032] <= sa32_sr_round2 ^ w2[07:00];
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text_out[007:000] <= sa33_sr_round2 ^ w3[07:00];
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text_out[007:000] <= sa33_sr_round2 ^ w3[07:00];
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end
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end
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always @(posedge clk)
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/* -----\/----- EXCLUDED -----\/-----
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begin
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always @(posedge clk)
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/* $strobe($time,": text_out_temp is %h\n",text_out_temp);
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begin
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/-* $strobe($time,": text_out_temp is %h\n",text_out_temp);
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*/ /*
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*-/ /-*
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$strobe($time,": subbytes is %h\n",{sa00_sub, sa01_sub, sa02_sub, sa03_sub,
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$strobe($time,": subbytes is %h\n",{sa00_sub, sa01_sub, sa02_sub, sa03_sub,
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sa10_sub, sa11_sub, sa12_sub, sa13_sub,
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sa10_sub, sa11_sub, sa12_sub, sa13_sub,
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sa20_sub, sa21_sub, sa22_sub, sa23_sub,
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sa20_sub, sa21_sub, sa22_sub, sa23_sub,
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sa30_sub, sa31_sub, sa32_sub, sa33_sub});
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sa30_sub, sa31_sub, sa32_sub, sa33_sub});
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Line 425... |
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$strobe($time,": mixcolumn_e is %h\n",{sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2,
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$strobe($time,": mixcolumn_e is %h\n",{sa00_mc_round2, sa01_mc_round2, sa02_mc_round2, sa03_mc_round2,
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sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2,
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sa10_mc_round2, sa11_mc_round2, sa12_mc_round2, sa13_mc_round2,
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sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2,
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sa20_mc_round2, sa21_mc_round2, sa22_mc_round2, sa23_mc_round2,
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sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2});
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sa30_mc_round2, sa31_mc_round2, sa32_mc_round2, sa33_mc_round2});
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*/
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*-/
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end
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end
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/*
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/-*
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if(done)
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if(done)
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begin
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begin
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text_out_64 <= text_out[127:64];
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text_out_64 <= text_out[127:64];
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// done2 <= 1;
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// done2 <= 1;
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end
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end
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else if(~done)
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else if(~done)
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text_out_64 <= text_out[63:0];
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text_out_64 <= text_out[63:0];
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end
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end
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*/
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*-/
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/*
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/-*
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if(done2)
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if(done2)
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begin
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begin
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text_out_64 <= text_out[63:0];
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text_out_64 <= text_out[63:0];
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end
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end
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end
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end
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*/
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*-/
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-----/\----- EXCLUDED -----/\----- */
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Generic Functions
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// Generic Functions
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//
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//
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