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--*************************************************************************
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-- Project : AES128 *
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-- *
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-- Block Name : README.txt *
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-- *
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-- Author : Hemanth Satyanarayana *
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-- *
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-- Email : hemanth@opencores.org *
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-- *
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-- Description: General Readme file *
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-- *
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-- . *
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-- *
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-- Revision History *
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Name | Date | Version | Revision details |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- | Hemanth | 15-Dec-2004 | 1.1.1.1 | Uploaded |*
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-- |-----------|-------------|---------|---------------------------------|*
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-- *
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-- Refer FIPS-197 document for details *
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--*************************************************************************
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-- *
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-- Copyright (C) 2004 Author *
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-- *
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-- This source file may be used and distributed without *
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-- restriction provided that this copyright statement is not *
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-- removed from the file and that any derivative work contains *
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-- the original copyright notice and the associated disclaimer. *
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-- *
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-- This source file is free software; you can redistribute it *
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-- and/or modify it under the terms of the GNU Lesser General *
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-- Public License as published by the Free Software Foundation; *
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-- either version 2.1 of the License, or (at your option) any *
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-- later version. *
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-- *
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-- This source is distributed in the hope that it will be *
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-- useful, but WITHOUT ANY WARRANTY; without even the implied *
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR *
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-- PURPOSE. See the GNU Lesser General Public License for more *
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-- details. *
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-- *
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-- You should have received a copy of the GNU Lesser General *
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-- Public License along with this source; if not, download it *
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-- from http://www.opencores.org/lgpl.shtml *
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-- *
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--*************************************************************************
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PROJECT AES128
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--------------
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This project is the hardware implementation of the
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Advanced Encryption Standard with a key size of 128 bits.
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The implementation adheres to the FIPS-197 document which explains the same.
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The core can do both encryption as well as decryption.
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The documents aes_arch.doc and aes_tb_readme.txt give further details of
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the rtl implementation and test bench respectively.
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This code was written originally with 128 bit ports for both input and key
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but later converted to 64 bits each to save on i/o pins. It can be reverted back
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easily if one just changes the port widths and dispenses with the load signal in
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the top module and making approriate changes in process where load is used.
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Synthesis results have been included for Xilinx Spartan-3 device.
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The directory structure of the project is as under-
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AES128
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------ DOC [Contains Fips document and architecture details]
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------ RTL [Contains RTL modules]
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------ SIM [Simulation folder containing test scripts and results]
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------ SYNTH [Synthesis related documents]
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------ TB [Test Bench modules and TB readme file]
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------ TB RESULTS [TB results stored here also]
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------ TB SCRIPTS [TB test scripts stored here also]
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------ README FILE [The file you are reading now]
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The verification is done generally in the simulation folder which should contain all the
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required test scripts. An additional simulation script called "aescomp&run.do" is included
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in the sim folder which can be used optionally to test the core if using ModelSim simulator.
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Else simulate the individual TBs from sim folder for the time mentioned in the above script.
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