OpenCores
URL https://opencores.org/ocsvn/aes_decrypt_fpga/aes_decrypt_fpga/trunk

Subversion Repositories aes_decrypt_fpga

[/] [aes_decrypt_fpga/] [trunk/] [bench/] [verilog/] [aes_decrypt192_tb.sv] - Diff between revs 2 and 3

Show entire file | Details | Blame | View Log

Rev 2 Rev 3
Line 1... Line 1...
 
////////////////////////////////////////////////////////////////// ////
 
////                                                                                                                            ////
 
//// AES Decryption Core for FPGA                                                                       ////
 
////                                                                                                                            ////
 
//// This file is part of the AES Decryption Core for FPGA project      ////
 
//// http://www.opencores.org/cores/xxx/                                                        ////
 
////                                                                                                                            ////
 
//// Description                                                                                                        ////
 
//// Implementation of  AES Decryption Core for FPGA according to       ////
 
//// core specification document.                                                                       ////
 
////                                                                                                                            ////
 
//// To Do:                                                                                                             ////
 
//// -                                                                                                                          ////
 
////                                                                                                                            ////
 
//// Author(s):                                                                                                         ////
 
//// - scheng, schengopencores@opencores.org                                            ////
 
////                                                                                                                            ////
 
//////////////////////////////////////////////////////////////////////
 
////                                                                                                                            ////
 
//// Copyright (C) 2009 Authors and OPENCORES.ORG                                       ////
 
////                                                                                                                            ////
 
//// This source file may be used and distributed without                       ////
 
//// restriction provided that this copyright statement is not          ////
 
//// removed from the file and that any derivative work contains        ////
 
//// the original copyright notice and the associated disclaimer.       ////
 
////                                                                                                                            ////
 
//// This source file is free software; you can redistribute it         ////
 
//// and/or modify it under the terms of the GNU Lesser General         ////
 
//// Public License as published by the Free Software Foundation;       ////
 
//// either version 2.1 of the License, or (at your option) any         ////
 
//// later version.                                                                                             ////
 
////                                                                                                                            ////
 
//// This source is distributed in the hope that it will be             ////
 
//// useful, but WITHOUT ANY WARRANTY; without even the implied         ////
 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ////
 
//// PURPOSE. See the GNU Lesser General Public License for more        ////
 
//// details.                                                                                                           ////
 
////                                                                                                                            ////
 
//// You should have received a copy of the GNU Lesser General          ////
 
//// Public License along with this source; if not, download it         ////
 
//// from http://www.opencores.org/lgpl.shtml                                           ////
 
////                                                                                                                            //// ///
 
///////////////////////////////////////////////////////////////////
 
////                                                                                                                            ////
 
//// Testbench for 192-bit decryption                                                           ////
 
////                                                                                                                            ////
 
////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
`timescale 1ns/1ps
 
 
// Uncomment the following line if you're targetting Xilinx FPGA
// Uncomment the following line if you're targetting Xilinx FPGA
//`define XILINX 1
//`define XILINX 1
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.