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----------------------------------------------------------------------
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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--
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-- Description: The Overall Core
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-- Ports:
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-- clk_i: System Clock
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-- plaintext_i: Input plaintext blocks
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-- keyblock_i: Input keyblock
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-- ciphertext_o: Output Cipher Block
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------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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use IEEE.std_logic_unsigned.all;
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library work;
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use work.aes_pkg.all;
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entity aes_top is
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port(
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clk_i: in std_logic;
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plaintext_i: in datablock;
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keyblock_i: in datablock;
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ciphertext_o: out datablock
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);
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end aes_top;
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architecture rtl of aes_top is
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signal fc3, c0, c1, c2, c3: colnet(9 downto 0);
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signal textnet_a_s, textnet_s_m, textnet_m_a: datanet(9 downto 0);
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signal key_m, key_s: datanet(9 downto 0);
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signal textnet_s_a: datablock;
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component sboxshr is
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port(
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clk: in std_logic;
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blockin: in datablock;
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fc3: in blockcol;
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c0: in blockcol;
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c1: in blockcol;
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c2: in blockcol;
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c3: in blockcol;
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nextkey: out datablock;
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blockout: out datablock
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);
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end component;
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component colmix is
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port(
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clk: in std_logic;
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datain: in datablock;
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inrkey: in datablock;
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outrkey: out datablock;
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dataout: out datablock
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);
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end component;
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component addkey is
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port(
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clk: in std_logic;
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roundkey: in datablock;
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datain: in datablock;
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rcon: in std_logic_vector(7 downto 0);
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dataout: out datablock;
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fc3: out blockcol;
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c0: out blockcol;
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c1: out blockcol;
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c2: out blockcol;
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c3: out blockcol
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);
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end component;
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begin
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key_m(0) <= keyblock_i;
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textnet_m_a(0) <= plaintext_i;
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-------------------------------------------------------
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-- Instead of the conventional order of
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-- Addkey -> (Sbox -> Mixcol -> Addkey) ... 9 times
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-- -> Sbox -> Addkey, we code the design as
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-- (Addkey -> Sbox -> Mixcol) ... 9 times -> Addkey ->
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-- Sbox -> Addkey
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-------------------------------------------------------
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proc: for i in 8 downto 0 generate
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add: addkey port map(
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clk => clk_i,
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roundkey => key_m(i),
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datain => textnet_m_a(i),
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rcon => rcon(i),
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dataout => textnet_a_s(i),
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fc3 => fc3(i),
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c0 => c0(i),
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c1 => c1(i),
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c2 => c2(i),
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c3 => c3(i)
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);
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sbox: sboxshr port map(
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clk => clk_i,
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blockin => textnet_a_s(i),
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fc3 => fc3(i),
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c0 => c0(i),
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c1 => c1(i),
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c2 => c2(i),
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c3 => c3(i),
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nextkey => key_s(i),
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blockout => textnet_s_m(i)
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);
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mix: colmix port map(
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clk => clk_i,
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datain => textnet_s_m(i),
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inrkey => key_s(i),
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outrkey => key_m(i+1),
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dataout => textnet_m_a(i+1)
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);
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end generate;
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add_f_1: addkey port map(
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clk => clk_i,
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roundkey => key_m(9),
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datain => textnet_m_a(9),
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rcon => rcon(9),
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dataout => textnet_a_s(9),
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fc3 => fc3(9),
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c0 => c0(9),
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c1 => c1(9),
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c2 => c2(9),
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c3 => c3(9)
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);
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sbox_f_1: sboxshr port map(
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clk => clk_i,
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blockin => textnet_a_s(9),
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fc3 => fc3(9),
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c0 => c0(9),
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c1 => c1(9),
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c2 => c2(9),
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c3 => c3(9),
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nextkey => key_s(9),
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blockout => textnet_s_a
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);
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add_f: addkey port map(
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clk => clk_i,
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roundkey => key_s(9),
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datain => textnet_s_a,
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rcon => X"00",
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dataout => ciphertext_o
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);
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end rtl;
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