| Line 42... |
Line 42... |
---- ----
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---- ----
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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------------------------------------------------------
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------------------------------------------------------
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-- Project: AESFast
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-- Project: AESFast
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-- Author: Subhasis
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-- Author: Subhasis
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-- Last Modified: 20/03/10
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-- Last Modified: 25/03/10
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-- Email: subhasis256@gmail.com
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-- Email: subhasis256@gmail.com
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------------------------------------------------------
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------------------------------------------------------
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--
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--
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-- Description: The Sbox and Shiftrows step
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-- Description: The Sbox and Shiftrows step
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-- Ports:
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-- Ports:
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| Line 70... |
Line 70... |
use work.aes_pkg.all;
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use work.aes_pkg.all;
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|
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entity sboxshr is
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entity sboxshr is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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blockin: in datablock;
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blockin: in datablock;
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fc3: in blockcol;
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fc3: in blockcol;
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c0: in blockcol;
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c0: in blockcol;
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c1: in blockcol;
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c1: in blockcol;
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c2: in blockcol;
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c2: in blockcol;
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| Line 85... |
Line 86... |
|
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architecture rtl of sboxshr is
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architecture rtl of sboxshr is
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component sbox is
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component sbox is
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port(
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port(
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clk: in std_logic;
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clk: in std_logic;
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rst: in std_logic;
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bytein: in std_logic_vector(7 downto 0);
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bytein: in std_logic_vector(7 downto 0);
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byteout: out std_logic_vector(7 downto 0)
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byteout: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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begin
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begin
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-- The sbox, the output going to the appropriate state byte after shiftrows
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-- The sbox, the output going to the appropriate state byte after shiftrows
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g0: for i in 3 downto 0 generate
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g0: for i in 3 downto 0 generate
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g1: for j in 3 downto 0 generate
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g1: for j in 3 downto 0 generate
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sub: sbox port map(
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sub: sbox port map(
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clk => clk,
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clk => clk,
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rst => rst,
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bytein => blockin(i,j),
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bytein => blockin(i,j),
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byteout => blockout(i,(j-i) mod 4)
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byteout => blockout(i,(j-i) mod 4)
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);
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);
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end generate;
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end generate;
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end generate;
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end generate;
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process(clk)
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process(clk,rst)
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begin
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begin
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if(rising_edge(clk)) then
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if(rst = '1') then
|
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nextkey <= zero_data;
|
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elsif(rising_edge(clk)) then
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-- col0 of nextkey = fc3 xor col0
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-- col0 of nextkey = fc3 xor col0
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-- col1 of nextkey = fc3 xor col0 xor col1
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-- col1 of nextkey = fc3 xor col0 xor col1
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-- col2 of nextkey = fc3 xor col0 xor col1 xor col2
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-- col2 of nextkey = fc3 xor col0 xor col1 xor col2
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-- col3 of nextkey = fc3 xor col0 xor col1 xor col2 xor col3
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-- col3 of nextkey = fc3 xor col0 xor col1 xor col2 xor col3
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genkey: for j in 3 downto 0 loop
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genkey: for j in 3 downto 0 loop
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