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https://opencores.org/ocsvn/ahb_slave/ahb_slave/trunk
[/] [ahb_slave/] [trunk/] [src/] [base/] [ahb_slave_ram.v] - Diff between revs 2 and 3
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| Rev 2 |
Rev 3 |
| Line 39... |
Line 39... |
reg HRESP;
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reg HRESP;
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reg timeout_stall;
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reg timeout_stall;
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reg [1:0] HSIZE_d;
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reg [1:0] HSIZE_d;
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wire WR_pre;
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wire WR_pre;
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reg WR_pre_d;
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wire WR;
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wire [ADDR_BITS-1:0] ADDR_WR_pre;
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wire [ADDR_BITS-1:0] ADDR_WR_pre;
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reg WR;
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reg [ADDR_BITS-1:0] ADDR_WR;
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reg [ADDR_BITS-1:0] ADDR_WR;
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reg data_phase;
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reg data_phase;
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wire [7:0] BSEL_wide;
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wire [7:0] BSEL_wide;
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| Line 131... |
Line 132... |
assign HRDATA = HREADY & data_phase ? DOUT : 'd0;
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assign HRDATA = HREADY & data_phase ? DOUT : 'd0;
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assign HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);
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assign HREADY = HTRANS == TRANS_STALL ? 1'b0 : (~timeout_stall) & (~STALL);
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assign WR_pre = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ));
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assign WR_pre = HWRITE & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ));
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assign WR = WR_pre_d & HREADY;
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assign RD = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY;
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assign RD = (~HWRITE) & ((HTRANS == TRANS_NONSEQ) | (HTRANS == TRANS_SEQ)) & HREADY;
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assign ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;
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assign ADDR_WR_pre = {ADDR_BITS{WR_pre}} & HADDR;
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assign ADDR_RD = {ADDR_BITS{RD}} & HADDR;
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assign ADDR_RD = {ADDR_BITS{RD}} & HADDR;
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assign DIN = HWDATA;
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assign DIN = HWDATA;
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| Line 166... |
Line 168... |
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always @(posedge clk or posedge reset)
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always @(posedge clk or posedge reset)
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if (reset)
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if (reset)
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begin
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begin
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WR <= #FFD 1'b0;
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WR_pre_d <= #FFD 1'b0;
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ADDR_WR <= #FFD {ADDR_BITS{1'b0}};
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ADDR_WR <= #FFD {ADDR_BITS{1'b0}};
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HSIZE_d <= #FFD 2'b0;
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HSIZE_d <= #FFD 2'b0;
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end
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end
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else if (HREADY)
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else if (HREADY)
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begin
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begin
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WR <= #FFD WR_pre;
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WR_pre_d <= #FFD WR_pre;
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ADDR_WR <= #FFD ADDR_WR_pre;
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ADDR_WR <= #FFD ADDR_WR_pre;
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HSIZE_d <= #FFD HSIZE;
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HSIZE_d <= #FFD HSIZE;
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end
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end
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