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Line 37... |
// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "global_defines.v"
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`include "global_defines.vh"
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module a23_decode
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module a23_decode
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(
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(
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input i_clk,
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input i_clk,
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input [31:0] i_read_data,
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input [31:0] i_read_data,
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Line 128... |
output [7:0] o_dabt_status
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output [7:0] o_dabt_status
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);
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);
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`include "a23_localparams.v"
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`include "a23_localparams.vh"
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`include "a23_functions.v"
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`include "a23_functions.vh"
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localparam [4:0] RST_WAIT1 = 5'd0,
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localparam [4:0] RST_WAIT1 = 5'd0,
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RST_WAIT2 = 5'd1,
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RST_WAIT2 = 5'd1,
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INT_WAIT1 = 5'd2,
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INT_WAIT1 = 5'd2,
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INT_WAIT2 = 5'd3,
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INT_WAIT2 = 5'd3,
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| Line 665... |
Line 665... |
barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
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barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
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if ( !immediate_shifter_operand && !instruction[4] )
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if ( !immediate_shifter_operand && !instruction[4] )
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barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
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barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
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// regops that do not change the overflow flag
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if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
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opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
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status_bits_sel_nxt = 3'd5;
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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end
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end
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Line 855... |
// Load or store ?
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// Load or store ?
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if ( !instruction[20] ) // Store
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if ( !instruction[20] ) // Store
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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// DOnt use mtrans_r15 here because its not loaded yet
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// Don't use mtrans_r15 here because its not loaded yet
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if ( {instruction[22:20],instruction[15]} == 4'b1010 )
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if ( {instruction[22],instruction[20],instruction[15]} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 3'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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// update the base register ?
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// update the base register ?
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if ( instruction[21] ) // the W bit
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if ( instruction[21] ) // the W bit
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reg_bank_wsel_nxt = o_rn_sel_nxt;
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reg_bank_wsel_nxt = o_rn_sel_nxt;
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Line 1057... |
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if ( !instruction[20] ) // Store
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if ( !instruction[20] ) // Store
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
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if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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end
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end
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end
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end
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Line 1088... |
end
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end
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else // Store
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else // Store
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
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if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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end
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end
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// second or fourth cycle of multiple load or store
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// second or fourth cycle of multiple load or store
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Line 1110... |
// the last register in the set to be loaded
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// the last register in the set to be loaded
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if ( instruction[20] && !dabt ) // Load
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if ( instruction[20] && !dabt ) // Load
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reg_bank_wsel_nxt = mtrans_reg_d2;
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reg_bank_wsel_nxt = mtrans_reg_d2;
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
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if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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//if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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end
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end
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// state is used for LMD/STM of a single register
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// state is used for LMD/STM of a single register
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if ( control_state == MTRANS_EXEC3B && instruction_execute )
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if ( control_state == MTRANS_EXEC3B && instruction_execute )
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Line 1130... |
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address_sel_nxt = 4'd3; // pc (not pc + 4)
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address_sel_nxt = 4'd3; // pc (not pc + 4)
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pc_wen_nxt = 1'd0; // hold current PC value
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pc_wen_nxt = 1'd0; // hold current PC value
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
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if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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end
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end
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if ( control_state == MTRANS_EXEC4 )
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if ( control_state == MTRANS_EXEC4 )
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begin
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begin
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Line 1184... |
begin
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begin
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pc_wen_nxt = 1'd0; // hold current PC value
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pc_wen_nxt = 1'd0; // hold current PC value
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end
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end
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// LDM: load into user mode registers, when in priviledged mode
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// LDM: load into user mode registers, when in priviledged mode
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if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
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if ( {instruction[22],instruction[20],mtrans_r15} == 3'b110 )
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user_mode_regs_load_nxt = 1'd1;
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user_mode_regs_load_nxt = 1'd1;
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// SDM: store the user mode registers, when in priviledged mode
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// SDM: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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end
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end
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// state is for when a data abort interrupt is triggered during an LDM
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// state is for when a data abort interrupt is triggered during an LDM
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Line 1639... |
// ========================================================
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// ========================================================
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// Decompiler for debugging core - not synthesizable
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// Decompiler for debugging core - not synthesizable
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// ========================================================
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// ========================================================
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//synopsys translate_off
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//synopsys translate_off
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`include "debug_functions.v"
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`include "debug_functions.vh"
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a23_decompile u_decompile (
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a23_decompile u_decompile (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_fetch_stall ( i_fetch_stall ),
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.i_fetch_stall ( i_fetch_stall ),
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.i_instruction ( instruction ),
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.i_instruction ( instruction ),
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