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// This file is part of the Amber project //
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// This file is part of the Amber project //
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// http://www.opencores.org/project,amber //
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// http://www.opencores.org/project,amber //
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// //
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// //
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// Description //
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// Description //
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// Instantiates the core consisting of fetch, instruction //
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// Instantiates the core consisting of fetch, instruction //
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// decode, execute, and co-processor. //
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// decode, execute, memory access and write back. The //
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// Wishbone interface and Co-Processor modules are also //
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// instantiated here. //
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// //
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// //
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// Author(s): //
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// Author(s): //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// - Conor Santifort, csantifort.amber@gmail.com //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress
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wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress
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// to the data cache rams
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// to the data cache rams
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wire [31:0] write_data;
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wire [31:0] write_data;
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wire write_enable;
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wire write_enable;
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wire [31:0] fetch_instruction;
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wire [31:0] fetch_instruction;
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// wire priviledged;
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wire decode_exclusive;
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wire decode_exclusive;
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wire decode_iaccess;
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wire decode_iaccess;
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wire decode_daccess;
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wire decode_daccess;
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wire [3:0] byte_enable;
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wire [3:0] byte_enable;
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wire exclusive; // swap access
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wire exclusive; // swap access
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wire [3:0] daddress_sel;
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wire [3:0] daddress_sel;
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wire [2:0] pc_sel;
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wire [2:0] pc_sel;
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wire [1:0] byte_enable_sel;
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wire [1:0] byte_enable_sel;
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wire [2:0] status_bits_sel;
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wire [2:0] status_bits_sel;
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wire [2:0] reg_write_sel;
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wire [2:0] reg_write_sel;
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// wire user_mode_regs_load;
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wire user_mode_regs_store_nxt;
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wire user_mode_regs_store_nxt;
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wire firq_not_user_mode;
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wire firq_not_user_mode;
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wire write_data_wen;
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wire write_data_wen;
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wire copro_write_data_wen;
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wire copro_write_data_wen;
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.o_daddress_sel ( daddress_sel ),
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.o_daddress_sel ( daddress_sel ),
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.o_pc_sel ( pc_sel ),
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.o_pc_sel ( pc_sel ),
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.o_byte_enable_sel ( byte_enable_sel ),
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.o_byte_enable_sel ( byte_enable_sel ),
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.o_status_bits_sel ( status_bits_sel ),
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.o_status_bits_sel ( status_bits_sel ),
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.o_reg_write_sel ( reg_write_sel ),
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.o_reg_write_sel ( reg_write_sel ),
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// .o_user_mode_regs_load ( user_mode_regs_load ),
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.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.o_firq_not_user_mode ( firq_not_user_mode ),
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.o_firq_not_user_mode ( firq_not_user_mode ),
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.o_write_data_wen ( write_data_wen ),
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.o_write_data_wen ( write_data_wen ),
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.o_base_address_wen ( base_address_wen ),
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.o_base_address_wen ( base_address_wen ),
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.o_pc_wen ( pc_wen ),
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.o_pc_wen ( pc_wen ),
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.i_daddress_sel ( daddress_sel ),
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.i_daddress_sel ( daddress_sel ),
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.i_pc_sel ( pc_sel ),
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.i_pc_sel ( pc_sel ),
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.i_byte_enable_sel ( byte_enable_sel ),
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.i_byte_enable_sel ( byte_enable_sel ),
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.i_status_bits_sel ( status_bits_sel ),
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.i_status_bits_sel ( status_bits_sel ),
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.i_reg_write_sel ( reg_write_sel ),
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.i_reg_write_sel ( reg_write_sel ),
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// .i_user_mode_regs_load ( user_mode_regs_load ),
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.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
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.i_firq_not_user_mode ( firq_not_user_mode ),
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.i_firq_not_user_mode ( firq_not_user_mode ),
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.i_write_data_wen ( write_data_wen ),
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.i_write_data_wen ( write_data_wen ),
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.i_base_address_wen ( base_address_wen ),
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.i_base_address_wen ( base_address_wen ),
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.i_pc_wen ( pc_wen ),
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.i_pc_wen ( pc_wen ),
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