OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [amber25/] [a25_decode.v] - Diff between revs 35 and 53

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 35 Rev 53
Line 296... Line 296...
wire                   irq_request;
wire                   irq_request;
wire                   swi_request;
wire                   swi_request;
wire                   und_request;
wire                   und_request;
wire                   dabt_request;
wire                   dabt_request;
reg    [1:0]           copro_operation_nxt;
reg    [1:0]           copro_operation_nxt;
reg                    mtrans_r15 = 'd0;
 
reg                    mtrans_r15_nxt;
 
reg                    restore_base_address = 'd0;
reg                    restore_base_address = 'd0;
reg                    restore_base_address_nxt;
reg                    restore_base_address_nxt;
 
 
wire                   regop_set_flags;
wire                   regop_set_flags;
 
 
Line 726... Line 724...
    copro_operation_nxt             = 'd0;
    copro_operation_nxt             = 'd0;
 
 
    // Save an instruction to use later
    // Save an instruction to use later
    saved_current_instruction_wen   = 1'd0;
    saved_current_instruction_wen   = 1'd0;
    pre_fetch_instruction_wen       = 1'd0;
    pre_fetch_instruction_wen       = 1'd0;
    mtrans_r15_nxt                  = mtrans_r15;
 
    restore_base_address_nxt        = restore_base_address;
    restore_base_address_nxt        = restore_base_address;
 
 
    // default Mux Select values
    // default Mux Select values
    barrel_shift_amount_sel_nxt     = 'd0;  // don't shift the input
    barrel_shift_amount_sel_nxt     = 'd0;  // don't shift the input
    barrel_shift_data_sel_nxt       = 'd0;  // immediate value
    barrel_shift_data_sel_nxt       = 'd0;  // immediate value
Line 947... Line 944...
        if ( type == MTRANS )
        if ( type == MTRANS )
            begin
            begin
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
            saved_current_instruction_wen   = 1'd1; // Save the memory access instruction to refer back to later
            decode_daccess_nxt              = 1'd1; // valid data access
            decode_daccess_nxt              = 1'd1; // valid data access
            alu_out_sel_nxt                 = 4'd1; // Add
            alu_out_sel_nxt                 = 4'd1; // Add
            mtrans_r15_nxt                  = instruction[15];  // load or save r15 ?
 
            base_address_wen_nxt            = 1'd1; // Save the value of the register used for the base address,
            base_address_wen_nxt            = 1'd1; // Save the value of the register used for the base address,
                                                    // in case of a data abort, and need to restore the value                        
                                                    // in case of a data abort, and need to restore the value                        
 
 
            if ( mtrans_num_registers > 4'd1 )
            if ( mtrans_num_registers > 4'd1 )
                begin
                begin
Line 1616... Line 1612...
        o_copro_crn                 <= instruction[19:16];
        o_copro_crn                 <= instruction[19:16];
        o_copro_crm                 <= instruction[3:0];
        o_copro_crm                 <= instruction[3:0];
        o_copro_num                 <= instruction[11:8];
        o_copro_num                 <= instruction[11:8];
        o_copro_operation           <= copro_operation_nxt;
        o_copro_operation           <= copro_operation_nxt;
        o_copro_write_data_wen      <= copro_write_data_wen_nxt;
        o_copro_write_data_wen      <= copro_write_data_wen_nxt;
        mtrans_r15                  <= mtrans_r15_nxt;
 
        restore_base_address        <= restore_base_address_nxt;
        restore_base_address        <= restore_base_address_nxt;
        control_state               <= control_state_nxt;
        control_state               <= control_state_nxt;
        end
        end
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.