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// You should have received a copy of the GNU Lesser General //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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// //
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//////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////
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`include "global_defines.v"
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`include "global_defines.vh"
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module a25_decode
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module a25_decode
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(
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(
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input i_clk,
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input i_clk,
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input [31:0] i_fetch_instruction,
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input [31:0] i_fetch_instruction,
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Line 129... |
output reg o_rs_use_read,
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output reg o_rs_use_read,
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output reg o_rd_use_read
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output reg o_rd_use_read
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);
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);
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`include "a25_localparams.v"
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`include "a25_localparams.vh"
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`include "a25_functions.v"
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`include "a25_functions.vh"
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localparam [4:0] RST_WAIT1 = 5'd0,
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localparam [4:0] RST_WAIT1 = 5'd0,
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RST_WAIT2 = 5'd1,
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RST_WAIT2 = 5'd1,
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INT_WAIT1 = 5'd2,
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INT_WAIT1 = 5'd2,
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INT_WAIT2 = 5'd3,
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INT_WAIT2 = 5'd3,
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branch ? 4'd15 : // Update the PC
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branch ? 4'd15 : // Update the PC
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rds_use_rs ? instruction[11:8] :
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rds_use_rs ? instruction[11:8] :
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instruction[15:12] ;
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instruction[15:12] ;
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// Load from memory into registers
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// Load from memory into registers
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assign ldm_user_mode = type == MTRANS && {instruction[22:20],instruction[15]} == 4'b1010;
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assign ldm_user_mode = type == MTRANS && {instruction[22],instruction[20],instruction[15]} == 3'b110;
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assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];
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assign ldm_flags = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22];
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assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;
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assign ldm_status_bits = type == MTRANS && rs_sel_nxt == 4'd15 && instruction[20] && instruction[22] && i_execute_status_bits[1:0] != USR;
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assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22];
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assign load_rd_byte = (type == TRANS || type == SWAP) && instruction[22];
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assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};
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assign load_rd_nxt = {ldm_flags, ldm_status_bits, ldm_user_mode, load_rd_byte, rs_sel_nxt};
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barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
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barrel_shift_amount_sel_nxt = 2'd1; // Shift amount from Rs registter
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if ( !immediate_shift_op && !instruction[4] )
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if ( !immediate_shift_op && !instruction[4] )
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barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
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barrel_shift_amount_sel_nxt = 2'd2; // Shift immediate amount
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// regops that do not change the overflow flag
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if ( opcode == AND || opcode == EOR || opcode == TST || opcode == TEQ ||
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opcode == ORR || opcode == MOV || opcode == BIC || opcode == MVN )
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status_bits_sel_nxt = 3'd5;
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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if ( opcode == ADD || opcode == CMN ) // CMN is just like an ADD
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begin
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begin
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alu_out_sel_nxt = 4'd1; // Add
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alu_out_sel_nxt = 4'd1; // Add
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end
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end
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// Load or store ?
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// Load or store ?
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if ( !instruction[20] ) // Store
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if ( !instruction[20] ) // Store
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// stm: store the user mode registers, when in priviledged mode
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// stm: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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// update the base register ?
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// update the base register ?
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if ( instruction[21] ) // the W bit
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if ( instruction[21] ) // the W bit
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reg_bank_wen_nxt = decode (rn_sel_nxt);
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reg_bank_wen_nxt = decode (rn_sel_nxt);
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Line 1208... |
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if ( !instruction[20] ) // Store
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if ( !instruction[20] ) // Store
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// stm: store the user mode registers, when in priviledged mode
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// stm: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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// write to the pc ?
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// write to the pc ?
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if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
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if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
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begin
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begin
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Line 1244... |
// Store
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// Store
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if ( !instruction[20] )
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if ( !instruction[20] )
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write_data_wen_nxt = 1'd1;
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write_data_wen_nxt = 1'd1;
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// stm: store the user mode registers, when in priviledged mode
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// stm: store the user mode registers, when in priviledged mode
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if ( {instruction[22:20]} == 3'b100 )
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if ( {instruction[22],instruction[20]} == 2'b10 )
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o_user_mode_regs_store_nxt = 1'd1;
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o_user_mode_regs_store_nxt = 1'd1;
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// write to the pc ?
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// write to the pc ?
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if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
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if ( instruction[20] && mtrans_reg1 == 4'd15 ) // Write to PC
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begin
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begin
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Line 1417... |
end
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end
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// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq
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// Speed up the long path from u_decode/fetch_instruction_r to u_register_bank/r8_firq
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// This pre-encodes the firq_s3 signal thats used in u_register_bank
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// This pre-encodes the firq_s3 signal thats used in u_register_bank
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// assign firq_not_user_mode_nxt = !user_mode_regs_load_nxt && status_bits_mode_nxt == FIRQ;
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assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ;
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assign firq_not_user_mode_nxt = status_bits_mode_nxt == FIRQ;
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// ========================================================
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// ========================================================
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// Next State Logic
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// Next State Logic
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Line 1710... |
// ========================================================
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// ========================================================
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// Decompiler for debugging core - not synthesizable
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// Decompiler for debugging core - not synthesizable
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// ========================================================
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// ========================================================
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//synopsys translate_off
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//synopsys translate_off
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`include "debug_functions.v"
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`include "debug_functions.vh"
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a25_decompile u_decompile (
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a25_decompile u_decompile (
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.i_clk ( i_clk ),
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.i_clk ( i_clk ),
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.i_core_stall ( i_core_stall ),
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.i_core_stall ( i_core_stall ),
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.i_instruction ( instruction ),
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.i_instruction ( instruction ),
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