OpenCores

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`// This file is part of the Amber project //`	`// This file is part of the Amber project //`
`// http://www.opencores.org/project,amber //`	`// http://www.opencores.org/project,amber //`
`// //`	`// //`
`// Description //`	`// Description //`
`// Turns memory access requests from the execute stage and //`	`// Turns memory access requests from the execute stage and //`
`// cache into wishbone bus cycles. For 4-word read requests //`	`// instruction and data caches into wishbone bus cycles. //`
`// from the cache and swap accesses ( read followed by write //`	`// For 4-word read requests from either cache and swap //`
`// to the same address) from the execute stage, //`	`// accesses ( read followed by write to the same address) //`
`// a block transfer is done. All other requests result in //`	`// from the execute stage, a block transfer is done. //`
`// single word transfers. //`	`// All other requests result in single word transfers. //`
`// //`	`// //`
`// Write accesses can be done in a single clock cycle on //`	`// Write accesses can be done in a single clock cycle on //`
`// the wishbone bus, is the destination allows it. The //`	`// the wishbone bus, is the destination allows it. The //`
`// next transfer will begin immediately on the //`	`// next transfer will begin immediately on the //`
`// next cycle on the bus. This looks like a block transfer //`	`// next cycle on the bus. This looks like a block transfer //`

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//  This file is part of the Amber project                      //

//  This file is part of the Amber project                      //

//  http://www.opencores.org/project,amber                      //

//  http://www.opencores.org/project,amber                      //

//                                                              //

//                                                              //

//  Description                                                 //

//  Description                                                 //

//  Turns memory access requests from the execute stage and     //

//  Turns memory access requests from the execute stage and     //

//  cache into wishbone bus cycles. For 4-word read requests    //

//  instruction and data caches into wishbone bus cycles.       //

//  from the cache and swap accesses ( read followed by write   //

//  For 4-word read requests from either cache and swap         //

//  to the same address) from the execute stage,                //

//  accesses ( read followed by write to the same address)      //

//  a block transfer is done. All other requests result in      //

//  from the execute stage, a block transfer is done.           //

//  single word transfers.                                      //

//  All other requests result in single word transfers.         //

//                                                              //

//                                                              //

//  Write accesses can be done in a single clock cycle on       //

//  Write accesses can be done in a single clock cycle on       //

//  the wishbone bus, is the destination allows it. The         //

//  the wishbone bus, is the destination allows it. The         //

//  next transfer will begin immediately on the                 //

//  next transfer will begin immediately on the                 //

//  next cycle on the bus. This looks like a block transfer     //

//  next cycle on the bus. This looks like a block transfer     //

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