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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] [wb_xs6_ddr3_bridge.v] - Diff between revs 2 and 11

Rev 2	Rev 11
Line 45...	Line 45...

`module wb_xs6_ddr3_bridge`	`module wb_xs6_ddr3_bridge`
`(`	`(`
`input i_clk,`	`input i_clk,`

	`input i_mem_ctrl, // 0=128MB, 1=32MB`

`// Wishbone Bus`	`// Wishbone Bus`
`input [31:0] i_wb_adr,`	`input [31:0] i_wb_adr,`
`input [3:0] i_wb_sel,`	`input [3:0] i_wb_sel,`
`input i_wb_we,`	`input i_wb_we,`
`output reg [31:0] o_wb_dat = 'd0,`	`output reg [31:0] o_wb_dat = 'd0,`
Line 75...	Line 77...
`wire start_write;`	`wire start_write;`
`wire start_read;`	`wire start_read;`
`reg start_write_d1;`	`reg start_write_d1;`
`reg start_read_d1;`	`reg start_read_d1;`
`reg start_read_hold = 'd0;`	`reg start_read_hold = 'd0;`
`reg [31:0] wb_adr_d1;`	`reg [29:0] wb_adr_d1;`
`wire ddr3_busy;`	`wire ddr3_busy;`
`reg read_ack = 'd0;`	`reg read_ack = 'd0;`
`reg read_ready = 1'd1;`	`reg read_ready = 1'd1;`


Line 128...	Line 130...
`else if ( start_read )`	`else if ( start_read )`
`read_ready <= 1'd0;`	`read_ready <= 1'd0;`

`start_write_d1 <= start_write;`	`start_write_d1 <= start_write;`
`start_read_d1 <= start_read;`	`start_read_d1 <= start_read;`
`wb_adr_d1 <= i_wb_adr;`	`wb_adr_d1 <= i_mem_ctrl ? {5'd0, i_wb_adr[24:0]} : i_wb_adr[29:0];`

`if ( start_read )`	`if ( start_read )`
`start_read_hold <= 1'd1;`	`start_read_hold <= 1'd1;`
`else if ( read_ack )`	`else if ( read_ack )`
`start_read_hold <= 1'd0;`	`start_read_hold <= 1'd0;`