URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Diff between revs 25 and 28

Rev 25	Rev 28
Line 1...	Line 1...
`All notable changes to this project will be documented in this file.`	`All notable changes to this project will be documented in this file.`


	`##[1.5.1] - 3-2-2017`
	`## changed`
	`- src_c/jtag_main.c: variable length memory support is added.`
	`- NoC emulator: Jtag tabs are reduced to total of 3. A 64 core 2-VC NoC emulation is sucessfully tested on DE4 FPGA board.`
	`-ssa: Now can work with fully adaptive routing.`


`##[1.5.0] - 13-10-2016`	`##[1.5.0] - 13-10-2016`
`### Added`	`### Added`
`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`	`- static straight allocator (SSA) which accelerates packets traversing to the same direction to the NoC router.`
`- NoC emulator.`	`- NoC emulator.`
`- Altor processor.`	`- Altor processor.`