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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [change.log] - Diff between revs 48 and 54

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Rev 48 Rev 54
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All notable changes to this project will be documented in this file.
All notable changes to this project will be documented in this file.
 
 
 
##[2.1.0] -26-03-2022
 
## added
 
- Multicast/Broadcast support
 
- SynFull traffic model is Integrated to NoC simulator
 
 
 
 
##[2.0.0] -15-10-2020
##[2.0.0] -15-10-2020
## added
## added
- SMART, single cycle multi hop bypass
- SMART, single cycle multi-hop bypass
- Selfloop suport
- Selfloop support
- gui for UART terminal
- gui for UART terminal
- gui for runtime memory controler
- gui for a runtime memory controller
- Suport Xilinx FPFAs
- Support Xilinx FPFAs
- Software Auto-generation using CAL language (CAL2C)
- Software Auto-generation using CAL language (CAL2C)
- Suport multitreading in Verilator-based NoC simulator
- Support multi threading in Verilator-based NoC simulator
- Intigrated netrace to NoC simulator
- Integrated Netrace to NoC simulator
- add new topologies: Fmesh
- add new topologies: Fmesh
- gui for custom noc topology generation
- gui for custom NoC topology generation
- GTK3 support
- GTK3 support
 
 
## changed
## changed
- NoC codes are changing to systemVerilog. Now it uses struct for router connection interface.
- NoC codes are changing to systemVerilog. Now it uses struct for router connection interface.
 
 
 
 
 
 
##[1.9.1] -24-07-2019
##[1.9.1] -24-07-2019
## changed
## changed
- Some bugs are fixed in jtag interface.
- Some bugs are fixed in jtag interface.
 
 
##[1.9.0] -30-04-2019
##[1.9.0] -30-04-2019

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