| Line 9... |
Line 9... |
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
################################################################################
|
################################################################################
|
|
|
$ipgen = bless( {
|
$ipgen = bless( {
|
'ports' => {
|
'ports' => {
|
's_cti_i' => {
|
'm_send_dat_i' => {
|
|
'range' => 'Dw-1 : 0',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'cti_i',
|
'intfc_port' => 'dat_i',
|
'range' => 'TAGw-1 : 0',
|
|
'intfc_name' => 'plug:wb_slave[0]'
|
|
},
|
|
'm_send_sel_o' => {
|
|
'intfc_port' => 'sel_o',
|
|
'type' => 'output',
|
|
'range' => 'SELw-1 : 0',
|
|
'intfc_name' => 'plug:wb_master[0]'
|
'intfc_name' => 'plug:wb_master[0]'
|
},
|
},
|
'm_receive_cyc_o' => {
|
's_addr_i' => {
|
'intfc_port' => 'cyc_o',
|
'intfc_port' => 'adr_i',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'range' => 'S_Aw-1 : 0',
|
|
'type' => 'input'
|
|
},
|
|
'm_receive_sel_o' => {
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '',
|
'range' => 'SELw-1 : 0',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'intfc_port' => 'sel_o'
|
},
|
},
|
'm_send_ack_i' => {
|
'flit_in_wr' => {
|
'intfc_port' => 'ack_i',
|
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'range' => ''
|
|
},
|
|
'flit_out_wr' => {
|
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_port' => 'flit_out_wr',
|
'intfc_port' => 'flit_in_wr'
|
'type' => 'output'
|
|
},
|
},
|
'm_send_stb_o' => {
|
'm_send_stb_o' => {
|
'intfc_port' => 'stb_o',
|
|
'type' => 'output',
|
|
'range' => '',
|
'range' => '',
|
|
'type' => 'output',
|
|
'intfc_port' => 'stb_o',
|
'intfc_name' => 'plug:wb_master[0]'
|
'intfc_name' => 'plug:wb_master[0]'
|
},
|
},
|
'm_receive_addr_o' => {
|
'clk' => {
|
'range' => 'M_Aw-1 : 0',
|
'intfc_port' => 'clk_i',
|
|
'intfc_name' => 'plug:clk[0]',
|
|
'range' => '',
|
|
'type' => 'input'
|
|
},
|
|
's_sel_i' => {
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'sel_i',
|
|
'type' => 'input',
|
|
'range' => 'SELw-1 : 0'
|
|
},
|
|
's_cyc_i' => {
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'cyc_i',
|
|
'type' => 'input',
|
|
'range' => ''
|
|
},
|
|
'm_receive_ack_i' => {
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_port' => 'adr_o',
|
'intfc_port' => 'ack_i',
|
'type' => 'output'
|
'type' => 'input',
|
|
'range' => ''
|
},
|
},
|
'flit_in' => {
|
's_ack_o' => {
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_port' => 'ack_o',
|
'range' => 'Fw-1 : 0',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'flit_in',
|
'range' => '',
|
'type' => 'input'
|
'type' => 'output'
|
},
|
},
|
'reset' => {
|
'reset' => {
|
'intfc_name' => 'plug:reset[0]',
|
|
'range' => '',
|
'range' => '',
|
|
'type' => 'input',
|
'intfc_port' => 'reset_i',
|
'intfc_port' => 'reset_i',
|
'type' => 'input'
|
'intfc_name' => 'plug:reset[0]'
|
},
|
},
|
's_dat_o' => {
|
's_dat_i' => {
|
'type' => 'output',
|
'intfc_port' => 'dat_i',
|
'intfc_port' => 'dat_o',
|
|
'range' => 'Dw-1 : 0',
|
|
'intfc_name' => 'plug:wb_slave[0]'
|
|
},
|
|
's_stb_i' => {
|
|
'intfc_port' => 'stb_i',
|
|
'type' => 'input',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'range' => ''
|
'range' => 'Dw-1 : 0',
|
|
'type' => 'input'
|
},
|
},
|
'current_x' => {
|
'm_send_ack_i' => {
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_port' => 'ack_i',
|
'range' => 'Xw-1 : 0',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'input',
|
'range' => '',
|
'intfc_port' => 'current_x'
|
'type' => 'input'
|
},
|
},
|
'm_receive_cti_o' => {
|
'm_receive_cti_o' => {
|
|
'range' => 'TAGw-1 : 0',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'cti_o',
|
'intfc_port' => 'cti_o',
|
'range' => 'TAGw-1 : 0',
|
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_name' => 'plug:wb_master[1]'
|
},
|
},
|
's_we_i' => {
|
'irq' => {
|
'intfc_port' => 'we_i',
|
'intfc_port' => 'int_o',
|
'type' => 'input',
|
'intfc_name' => 'plug:interrupt_peripheral[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'range' => '',
|
'range' => ''
|
'type' => 'output'
|
},
|
},
|
'm_receive_we_o' => {
|
'flit_out_wr' => {
|
'type' => 'output',
|
|
'intfc_port' => 'we_o',
|
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[1]'
|
'type' => 'output',
|
|
'intfc_port' => 'flit_out_wr',
|
|
'intfc_name' => 'socket:ni[0]'
|
},
|
},
|
'm_send_dat_i' => {
|
'credit_out' => {
|
'type' => 'input',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_port' => 'dat_i',
|
'intfc_port' => 'credit_out',
|
|
'type' => 'output',
|
|
'range' => 'V-1 : 0'
|
|
},
|
|
's_dat_o' => {
|
'range' => 'Dw-1 : 0',
|
'range' => 'Dw-1 : 0',
|
'intfc_name' => 'plug:wb_master[0]'
|
'type' => 'output',
|
|
'intfc_port' => 'dat_o',
|
|
'intfc_name' => 'plug:wb_slave[0]'
|
},
|
},
|
'flit_in_wr' => {
|
'flit_in' => {
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'flit_in_wr',
|
'range' => 'Fw-1 : 0',
|
'range' => '',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_name' => 'socket:ni[0]'
|
'intfc_port' => 'flit_in'
|
},
|
},
|
's_sel_i' => {
|
's_stb_i' => {
|
'range' => 'SELw-1 : 0',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'stb_i',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'sel_i'
|
'range' => ''
|
},
|
|
'm_send_we_o' => {
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'range' => '',
|
|
'type' => 'output',
|
|
'intfc_port' => 'we_o'
|
|
},
|
},
|
'flit_out' => {
|
'current_r_addr' => {
|
'intfc_port' => 'flit_out',
|
'intfc_port' => 'current_r_addr',
|
'type' => 'output',
|
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_name' => 'socket:ni[0]',
|
'range' => 'Fw-1 : 0'
|
'range' => 'RAw-1 : 0',
|
|
'type' => 'input'
|
},
|
},
|
'm_send_cti_o' => {
|
'm_send_addr_o' => {
|
'range' => 'TAGw-1 : 0',
|
'type' => 'output',
|
|
'range' => 'M_Aw-1 : 0',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'cti_o',
|
'intfc_port' => 'adr_o'
|
'type' => 'output'
|
|
},
|
},
|
'm_receive_stb_o' => {
|
'm_send_sel_o' => {
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'stb_o',
|
'range' => 'SELw-1 : 0',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_port' => 'sel_o'
|
},
|
},
|
'm_send_cyc_o' => {
|
'm_receive_we_o' => {
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'cyc_o',
|
|
'range' => '',
|
|
'intfc_name' => 'plug:wb_master[0]'
|
|
},
|
|
's_cyc_i' => {
|
|
'intfc_port' => 'cyc_i',
|
|
'type' => 'input',
|
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_slave[0]'
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'intfc_port' => 'we_o'
|
},
|
},
|
'm_send_addr_o' => {
|
'm_receive_cyc_o' => {
|
'range' => 'M_Aw-1 : 0',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'cyc_o',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'adr_o'
|
'range' => ''
|
},
|
},
|
'm_receive_dat_o' => {
|
'm_receive_dat_o' => {
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'range' => 'Dw-1 : 0',
|
'range' => 'Dw-1 : 0',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'dat_o'
|
'intfc_port' => 'dat_o',
|
},
|
'intfc_name' => 'plug:wb_master[1]'
|
's_dat_i' => {
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'range' => 'Dw-1 : 0',
|
|
'type' => 'input',
|
|
'intfc_port' => 'dat_i'
|
|
},
|
},
|
'm_receive_sel_o' => {
|
'm_send_cti_o' => {
|
'intfc_port' => 'sel_o',
|
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => 'TAGw-1 : 0',
|
'range' => 'SELw-1 : 0'
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'cti_o'
|
},
|
},
|
'clk' => {
|
'm_send_we_o' => {
|
'intfc_port' => 'clk_i',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'input',
|
'intfc_port' => 'we_o',
|
'intfc_name' => 'plug:clk[0]',
|
'type' => 'output',
|
'range' => ''
|
'range' => ''
|
},
|
},
|
'current_y' => {
|
's_cti_i' => {
|
|
'range' => 'TAGw-1 : 0',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'current_y',
|
'intfc_port' => 'cti_i',
|
'range' => 'Yw-1 : 0',
|
'intfc_name' => 'plug:wb_slave[0]'
|
'intfc_name' => 'socket:ni[0]'
|
|
},
|
},
|
'm_receive_ack_i' => {
|
'flit_out' => {
|
'range' => '',
|
'range' => 'Fw-1 : 0',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'output',
|
'type' => 'input',
|
'intfc_port' => 'flit_out',
|
'intfc_port' => 'ack_i'
|
'intfc_name' => 'socket:ni[0]'
|
},
|
},
|
's_addr_i' => {
|
's_we_i' => {
|
'intfc_port' => 'adr_i',
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'we_i',
|
'type' => 'input',
|
'type' => 'input',
|
'range' => 'S_Aw-1 : 0',
|
'range' => ''
|
'intfc_name' => 'plug:wb_slave[0]'
|
|
},
|
},
|
'credit_out' => {
|
'current_e_addr' => {
|
'range' => 'V-1 : 0',
|
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_port' => 'credit_out',
|
'intfc_port' => 'current_e_addr',
|
'type' => 'output'
|
'type' => 'input',
|
|
'range' => 'EAw-1 : 0'
|
},
|
},
|
's_ack_o' => {
|
'm_receive_stb_o' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'stb_o',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => '',
|
'range' => '',
|
'type' => 'output',
|
'type' => 'output'
|
'intfc_port' => 'ack_o'
|
|
},
|
},
|
'irq' => {
|
'm_send_cyc_o' => {
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_port' => 'int_o',
|
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:interrupt_peripheral[0]'
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'cyc_o'
|
},
|
},
|
'credit_in' => {
|
'credit_in' => {
|
'type' => 'input',
|
|
'intfc_port' => 'credit_in',
|
'intfc_port' => 'credit_in',
|
'intfc_name' => 'socket:ni[0]',
|
'intfc_name' => 'socket:ni[0]',
|
'range' => 'V-1 : 0'
|
'range' => 'V-1 : 0',
|
|
'type' => 'input'
|
|
},
|
|
'm_receive_addr_o' => {
|
|
'range' => 'M_Aw-1 : 0',
|
|
'type' => 'output',
|
|
'intfc_port' => 'adr_o',
|
|
'intfc_name' => 'plug:wb_master[1]'
|
}
|
}
|
},
|
},
|
'ports_order' => [
|
'parameters_order' => [
|
'reset',
|
'TOPOLOGY',
|
'clk',
|
'ROUTE_NAME',
|
'current_x',
|
'T1',
|
'current_y',
|
'T2',
|
'flit_out',
|
'T3',
|
'flit_out_wr',
|
'C',
|
'credit_in',
|
'V',
|
'flit_in',
|
'B',
|
'flit_in_wr',
|
'Fpay',
|
'credit_out',
|
'MAX_TRANSACTION_WIDTH',
|
's_dat_i',
|
'MAX_BURST_SIZE',
|
's_sel_i',
|
'DEBUG_EN',
|
's_addr_i',
|
'Dw',
|
's_cti_i',
|
'S_Aw',
|
's_stb_i',
|
'M_Aw',
|
's_cyc_i',
|
'TAGw',
|
's_we_i',
|
'SELw',
|
's_dat_o',
|
'Fw',
|
's_ack_o',
|
'CRC_EN',
|
'm_send_sel_o',
|
'RAw',
|
'm_send_addr_o',
|
'EAw'
|
'm_send_cti_o',
|
|
'm_send_stb_o',
|
|
'm_send_cyc_o',
|
|
'm_send_we_o',
|
|
'm_send_dat_i',
|
|
'm_send_ack_i',
|
|
'm_receive_sel_o',
|
|
'm_receive_dat_o',
|
|
'm_receive_addr_o',
|
|
'm_receive_cti_o',
|
|
'm_receive_stb_o',
|
|
'm_receive_cyc_o',
|
|
'm_receive_we_o',
|
|
'm_receive_ack_i',
|
|
'irq'
|
|
],
|
],
|
'sockets' => {
|
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
|
'ni' => {
|
'system_v' => '`define INCLUDE_TOPOLOGY_LOCALPARAM
|
'0' => {
|
`include "topology_localparam.v"',
|
'name' => 'ni'
|
'modules' => {
|
|
'header_flit_generator' => {},
|
|
'ni_master' => {},
|
|
'ni_vc_dma' => {},
|
|
'vc_wb_slave_registers' => {},
|
|
'ovc_status' => {}
|
},
|
},
|
'value' => 1,
|
'category' => 'NoC',
|
'ni' => {},
|
'system_h' => '#include
|
'type' => 'num',
|
#include "../phy_addr.h"
|
'connection_num' => 'single connection'
|
|
|
/* NI wb registers addresses
|
|
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
|
|
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,aT2_error_isr,got_pck_isr, save_done_isr,send_done_isr,aT2_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
|
|
2 : BURST_SIZE_WB_ADDR // The busrt size in words
|
|
|
|
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
|
|
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte
|
|
5 : SEND_DEST_WB_ADDR // The destination router address
|
|
6 : SEND_CTRL_WB_ADDR
|
|
|
|
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte
|
|
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte
|
|
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
|
|
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
|
|
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred
|
|
12 : ERROR_FLAGS // errors: {crc_miss_match,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
|
|
|
|
*/
|
|
#define COREID ${CORE_ID}
|
|
#define CORE_PHY_ADDR PHY_ADDR_ENDP_${CORE_ID}
|
|
|
|
|
|
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0
|
|
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1
|
|
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2
|
|
|
|
|
|
#define ${IP}_NUM_VCs ${V}
|
|
|
|
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3
|
|
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4
|
|
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5
|
|
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6
|
|
|
|
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7
|
|
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8
|
|
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9
|
|
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10
|
|
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11
|
|
#define ${IP}_ERROR_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE+48+(v<<6)))) //12
|
|
|
|
|
|
|
|
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
|
|
// assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,aT2_error_isr,got_pck_isr, save_done_isr,send_done_isr,aT2_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
|
|
|
|
|
|
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1)
|
|
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1)
|
|
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1)
|
|
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1)
|
|
#define ${IP}_got_aT2_error(v) ((${IP}_STATUS2_REG >> (8+v)) & 0x1)
|
|
|
|
#define SEND_DONE_INT_EN (1<<0)
|
|
#define SAVE_DONE_INT_EN (1<<1)
|
|
#define GOT_PCK_INT_EN (1<<2)
|
|
#define ERRORS_INT_EN (1<<3)
|
|
#define ALL_INT_EN (SEND_DONE_INT_EN | SAVE_DONE_INT_EN | GOT_PCK_INT_EN | ERRORS_INT_EN)
|
|
|
|
#define SEND_DONE_ISR (1<<4)
|
|
#define SAVE_DONE_ISR (1<<5)
|
|
#define GOT_PCK_ISR (1<<6)
|
|
#define ERRORS_ISR (1<<7)
|
|
|
|
|
|
|
|
//errors = {crc_miss_match,illegal_send_req,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
|
|
#define BUFF_OVER_FLOW_ERR (1<<0) // This error happens when the receiver allocated buffer size is smaller than the received packet size
|
|
#define SEND_DATA_SIZE_ERR (1<<1) // This error happens when the send data size is not set
|
|
#define BURST_SIZE_ERR (1<<2) // This error happens when the burst size is not set
|
|
#define ILLEGAL_SEND_REQ (1<<3) // This error happens when a new send request is received while the DMA is still busy sending previous packet
|
|
#define CRC_MISS_MATCH (1<<4) // This error happens when the received packet CRC miss match
|
|
|
|
//ack intrrupts functions
|
|
#define ${IP}_ack_send_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN |SEND_DONE_ISR))
|
|
#define ${IP}_ack_save_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | SAVE_DONE_ISR))
|
|
#define ${IP}_ack_got_pck_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | GOT_PCK_ISR))
|
|
#define ${IP}_ack_errors_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | ERRORS_ISR))
|
|
|
|
#define ${IP}_ack_all_isr() (${IP}_STATUS2_REG = ${IP}_STATUS2_REG)
|
|
|
|
|
|
struct SRC_INFOS{
|
|
unsigned char r; // reserved
|
|
unsigned char c; // message class
|
|
int16_t addr; // phy_addr
|
|
} ;
|
|
|
|
inline struct SRC_INFOS get_src_info(unsigned char v){
|
|
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&ni_RECEIVE_SRC_REG(v));
|
|
return src_info;
|
}
|
}
|
},
|
|
'module_name' => 'ni_master',
|
/*
|
'hdl_files' => [
|
The NI initializing function.
|
'/mpsoc/src_noc/arbiter.v',
|
The burst_size must be <= $MAX_BURST_SIZE
|
'/mpsoc/src_noc/flit_buffer.v',
|
send_int_en :1: enable the intrrupt when a packet is sent 0 : This intrrupt is disabled
|
'/mpsoc/src_noc/input_ports.v',
|
save_int_en : 1: enable the intrrupt when a recived packet is saved on internal buffer 0 : This intrrupt is disabled
|
'/mpsoc/src_noc/main_comp.v',
|
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled
|
'/mpsoc/src_noc/route_mesh.v',
|
|
'/mpsoc/src_noc/route_torus.v',
|
*/
|
'/mpsoc/src_noc/routing.v',
|
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_int_en, unsigned char save_int_en, unsigned char got_pck_int_en) {
|
'/mpsoc/src_peripheral/ni/ni_vc_dma.v',
|
${IP}_BURST_SIZE_REG = burst_size;
|
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v',
|
if(errors_int_en) ${IP}_STATUS2_REG |= ERRORS_INT_EN;
|
'/mpsoc/src_peripheral/ni/ni_master.v',
|
if(send_int_en) ${IP}_STATUS2_REG |= SEND_DONE_INT_EN;
|
'/mpsoc/src_peripheral/ni/ni_crc32.v'
|
if(save_int_en) ${IP}_STATUS2_REG |= SAVE_DONE_INT_EN;
|
],
|
if(got_pck_int_en) ${IP}_STATUS2_REG |= GOT_PCK_INT_EN;
|
'unused' => {
|
}
|
'plug:wb_slave[0]' => [
|
|
'err_o',
|
/*
|
'rty_o',
|
The NI message sent function:
|
'tag_i',
|
v: virtual channel number which this packet should be sent to
|
'bte_i'
|
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock
|
],
|
data_start_addr : The address pointer to the start location of the packet to be sent in the memory
|
'plug:wb_master[1]' => [
|
data_size: the message data size in words
|
'tag_o',
|
dest_phy_addr: the destination endpoint physical address. check phy_adr.h file for knowing each endpoint physical address
|
'rty_i',
|
|
'bte_o',
|
*/
|
'err_i',
|
|
'dat_i'
|
void ${IP}_transfer (unsigned int init_weight, unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_phy_addr){
|
],
|
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet
|
'plug:wb_master[0]' => [
|
|
'tag_o',
|
${IP}_SEND_DATA_SIZE_REG(v) = data_size;
|
'rty_i',
|
${IP}_SEND_START_ADDR_REG(v) = data_start_addr;
|
'dat_o',
|
${IP}_SEND_DEST_REG(v) = dest_phy_addr | (class_num<<16) | (init_weight<<24);
|
'bte_o',
|
|
'err_i'
|
}
|
]
|
|
},
|
/*
|
'description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf',
|
The NI message receiver function:
|
|
v: virtual channel number of the received packet
|
|
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in.
|
|
max_buffer_size : The allocated receive-memory buffer size in words.
|
|
*/
|
|
|
|
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){
|
|
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet
|
|
|
|
${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr;
|
|
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size;
|
|
${IP}_RECEIVE_CTRL_REG(v) = 1;
|
|
|
|
|
|
}',
|
'parameters' => {
|
'parameters' => {
|
'C' => {
|
'ROUTE_NAME' => {
|
'content' => '',
|
|
'info' => 'Parameter',
|
|
'default' => ' 4',
|
|
'global_param' => 'Parameter',
|
'global_param' => 'Parameter',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'redefine_param' => 1
|
'default' => '"XY" ',
|
|
'redefine_param' => 1,
|
|
'content' => '',
|
|
'info' => 'Parameter'
|
},
|
},
|
'Dw' => {
|
'Fpay' => {
|
'type' => 'Spin-button',
|
'global_param' => 'Parameter',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
'default' => '32',
|
'default' => '32',
|
'info' => 'wishbone_bus data width in bits.',
|
'redefine_param' => 1,
|
'content' => '32,256,8',
|
'content' => '',
|
'redefine_param' => 1
|
'info' => 'Parameter'
|
},
|
},
|
'SRC_ADR_HDR_WIDTH' => {
|
'TAGw' => {
|
|
'default' => '3',
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'content' => '',
|
'content' => '',
|
'default' => '8',
|
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'redefine_param' => 1
|
'redefine_param' => 1
|
},
|
},
|
'SELw' => {
|
'S_Aw' => {
|
|
'content' => '',
|
|
'info' => 'Parameter',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'type' => 'Fixed',
|
'default' => '8',
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'info' => 'Parameter',
|
'type' => 'Fixed'
|
'default' => '4',
|
|
'content' => ''
|
|
},
|
},
|
'DEBUG_EN' => {
|
'T3' => {
|
'redefine_param' => 1,
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Parameter',
|
'global_param' => 'Parameter',
|
'default' => ' 1',
|
'default' => ' 1',
|
|
'redefine_param' => 1,
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'content' => ''
|
'content' => ''
|
},
|
},
|
'NY' => {
|
'MAX_BURST_SIZE' => {
|
'content' => '',
|
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
|
'info' => 'Parameter',
|
'info' => 'Maximum burst size in words.
|
'default' => ' 4',
|
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
|
'global_param' => 'Parameter',
|
'redefine_param' => 1,
|
|
'default' => '16',
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Combo-box'
|
|
},
|
|
'M_Aw' => {
|
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'redefine_param' => 1
|
'default' => '32',
|
|
'redefine_param' => 1,
|
|
'content' => 'Dw',
|
|
'info' => 'Parameter'
|
},
|
},
|
'TOPOLOGY' => {
|
'DEBUG_EN' => {
|
'default' => '"MESH"',
|
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'content' => '',
|
'content' => '',
|
|
'redefine_param' => 1,
|
|
'default' => ' 1',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Parameter',
|
'global_param' => 'Parameter'
|
'redefine_param' => 1
|
|
},
|
},
|
'Fpay' => {
|
'SELw' => {
|
'type' => 'Fixed',
|
|
'global_param' => 'Parameter',
|
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'default' => ' 32',
|
|
'content' => '',
|
'content' => '',
|
'redefine_param' => 1
|
'redefine_param' => 1,
|
|
'default' => '4',
|
|
'type' => 'Fixed',
|
|
'global_param' => 'Localparam'
|
},
|
},
|
'S_Aw' => {
|
'Dw' => {
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Spin-button',
|
|
'default' => '32',
|
|
'redefine_param' => 1,
|
|
'content' => '32,256,8',
|
|
'info' => 'wishbone_bus data width in bits.'
|
|
},
|
|
'Fw' => {
|
|
'redefine_param' => 0,
|
'content' => '',
|
'content' => '',
|
'default' => '8',
|
'info' => undef,
|
'info' => 'Parameter',
|
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'redefine_param' => 1
|
'default' => '2+V+Fpay'
|
},
|
},
|
'CLASS_HDR_WIDTH' => {
|
'B' => {
|
'redefine_param' => 1,
|
'global_param' => 'Parameter',
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
|
'default' => ' 4',
|
|
'redefine_param' => 1,
|
'content' => '',
|
'content' => '',
|
'default' => '8',
|
|
'info' => 'Parameter'
|
'info' => 'Parameter'
|
},
|
},
|
'DST_ADR_HDR_WIDTH' => {
|
'CRC_EN' => {
|
'redefine_param' => 1,
|
'type' => 'Combo-box',
|
'type' => 'Fixed',
|
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'default' => '8',
|
'default' => '"NO"',
|
'info' => 'Parameter',
|
'redefine_param' => 1,
|
'content' => ''
|
'info' => 'The parameter can be selected as "YES" or "NO".
|
|
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ',
|
|
'content' => '"YES","NO"'
|
},
|
},
|
'NX' => {
|
'V' => {
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Parameter',
|
'global_param' => 'Parameter',
|
'info' => 'Parameter',
|
|
'default' => ' 4',
|
'default' => ' 4',
|
'content' => '',
|
|
'redefine_param' => 1
|
|
},
|
|
'ROUTE_NAME' => {
|
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'default' => '"XY" ',
|
'content' => ''
|
'content' => '',
|
|
'type' => 'Fixed',
|
|
'global_param' => 'Parameter'
|
|
},
|
|
'MAX_BURST_SIZE' => {
|
|
'type' => 'Combo-box',
|
|
'global_param' => 'Localparam',
|
|
'default' => '16',
|
|
'info' => 'Maximum burst size in words.
|
|
The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ',
|
|
'content' => '2,4,8,16,32,64,128,256,512,1024,2048',
|
|
'redefine_param' => 1
|
|
},
|
},
|
'M_Aw' => {
|
'RAw' => {
|
'default' => '32',
|
|
'info' => 'Parameter',
|
|
'content' => 'Dw',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Localparam',
|
'global_param' => 'Parameter',
|
'redefine_param' => 1
|
'default' => '16',
|
},
|
'redefine_param' => 0,
|
'Fw' => {
|
|
'content' => '',
|
|
'default' => '2+V+Fpay',
|
|
'info' => undef,
|
'info' => undef,
|
'global_param' => 'Localparam',
|
'content' => ''
|
'type' => 'Fixed',
|
|
'redefine_param' => 0
|
|
},
|
},
|
'TAGw' => {
|
'T2' => {
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed',
|
|
'content' => '',
|
'content' => '',
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'default' => '3',
|
|
'redefine_param' => 1
|
|
},
|
|
'ROUTING_HDR_WIDTH' => {
|
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'default' => '8',
|
'default' => ' 4',
|
'info' => 'Parameter',
|
'global_param' => 'Parameter',
|
'content' => '',
|
'type' => 'Fixed'
|
'type' => 'Fixed',
|
|
'global_param' => 'Localparam'
|
|
},
|
},
|
'Xw' => {
|
'T1' => {
|
|
'global_param' => 'Parameter',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Localparam',
|
'default' => ' 4',
|
'info' => undef,
|
'redefine_param' => 1,
|
'default' => 'log2(NX)',
|
|
'content' => '',
|
'content' => '',
|
'redefine_param' => 0
|
'info' => 'Parameter'
|
},
|
},
|
'CRC_EN' => {
|
'TOPOLOGY' => {
|
|
'global_param' => 'Parameter',
|
|
'type' => 'Fixed',
|
|
'default' => '"MESH"',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Localparam',
|
'content' => '',
|
'type' => 'Combo-box',
|
'info' => 'Parameter'
|
'content' => '"YES","NO"',
|
|
'default' => '"NO"',
|
|
'info' => 'The parameter can be selected as "YES" or "NO".
|
|
If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. '
|
|
},
|
},
|
'Yw' => {
|
'EAw' => {
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => '',
|
'content' => '',
|
'info' => undef,
|
'info' => undef,
|
'default' => 'log2(NY)',
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed'
|
|
},
|
|
'V' => {
|
|
'content' => '',
|
|
'default' => '4',
|
|
'info' => 'Parameter',
|
|
'global_param' => 'Parameter',
|
'global_param' => 'Parameter',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'redefine_param' => 1
|
'default' => '16'
|
},
|
},
|
'B' => {
|
'C' => {
|
'content' => '',
|
|
'info' => 'Parameter',
|
|
'default' => ' 4',
|
'default' => ' 4',
|
'global_param' => 'Parameter',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
|
'global_param' => 'Parameter',
|
|
'info' => 'Parameter',
|
|
'content' => '',
|
'redefine_param' => 1
|
'redefine_param' => 1
|
},
|
},
|
'MAX_TRANSACTION_WIDTH' => {
|
'MAX_TRANSACTION_WIDTH' => {
|
'content' => '4,32,1',
|
|
'default' => '13',
|
'default' => '13',
|
'info' => 'maximum packet size width in words.
|
|
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Spin-button',
|
'type' => 'Spin-button',
|
'redefine_param' => 1
|
'global_param' => 'Localparam',
|
}
|
'info' => 'maximum packet size width in words.
|
},
|
The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.',
|
'modules' => {
|
'content' => '4,32,1',
|
'vc_wb_slave_registers' => {},
|
'redefine_param' => 1
|
'ovc_status' => {},
|
}
|
'header_flit_generator' => {},
|
},
|
'ni_master' => {},
|
|
'ni_vc_dma' => {}
|
|
},
|
|
'category' => 'NoC',
|
|
'parameters_order' => [
|
|
'CLASS_HDR_WIDTH',
|
|
'ROUTING_HDR_WIDTH',
|
|
'DST_ADR_HDR_WIDTH',
|
|
'SRC_ADR_HDR_WIDTH',
|
|
'TOPOLOGY',
|
|
'ROUTE_NAME',
|
|
'NX',
|
|
'NY',
|
|
'C',
|
|
'V',
|
|
'B',
|
|
'Fpay',
|
|
'MAX_TRANSACTION_WIDTH',
|
|
'MAX_BURST_SIZE',
|
|
'DEBUG_EN',
|
|
'Dw',
|
|
'S_Aw',
|
|
'M_Aw',
|
|
'TAGw',
|
|
'SELw',
|
|
'Xw',
|
|
'Yw',
|
|
'Fw',
|
|
'CRC_EN'
|
|
],
|
|
'plugs' => {
|
'plugs' => {
|
'clk' => {
|
'wb_master' => {
|
|
'type' => 'num',
|
'0' => {
|
'0' => {
|
'name' => 'clk'
|
'name' => 'wb_send'
|
|
},
|
|
'value' => 2,
|
|
'1' => {
|
|
'name' => 'wb_receive'
|
|
},
|
|
'wb_master' => {}
|
},
|
},
|
'clk' => {},
|
'interrupt_peripheral' => {
|
'type' => 'num',
|
'type' => 'num',
|
'value' => 1
|
'0' => {
|
|
'name' => 'interrupt'
|
|
},
|
|
'value' => 1,
|
|
'interrupt_peripheral' => {}
|
},
|
},
|
'reset' => {
|
'reset' => {
|
'0' => {
|
'0' => {
|
'name' => 'reset'
|
'name' => 'reset'
|
},
|
},
|
|
'value' => 1,
|
'type' => 'num',
|
'type' => 'num',
|
'reset' => {},
|
'reset' => {}
|
'value' => 1
|
|
},
|
},
|
'wb_slave' => {
|
'wb_slave' => {
|
'wb_slave' => {},
|
'wb_slave' => {},
|
'type' => 'num',
|
|
'value' => 1,
|
'value' => 1,
|
'0' => {
|
'0' => {
|
'name' => 'wb_slave',
|
'addr' => '0xb800_0000 0xbfff_ffff custom devices',
|
'width' => 10,
|
'width' => 10,
|
'addr' => '0xb800_0000 0xbfff_ffff custom devices'
|
'name' => 'wb_slave'
|
}
|
|
},
|
|
'interrupt_peripheral' => {
|
|
'value' => 1,
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'interrupt'
|
|
},
|
},
|
'interrupt_peripheral' => {}
|
'type' => 'num'
|
},
|
},
|
'wb_master' => {
|
'clk' => {
|
|
'type' => 'num',
|
'0' => {
|
'0' => {
|
'name' => 'wb_send'
|
'name' => 'clk'
|
},
|
},
|
'wb_master' => {},
|
'value' => 1,
|
'type' => 'num',
|
'clk' => {}
|
'value' => 2,
|
|
'1' => {
|
|
'name' => 'wb_receive'
|
|
}
|
|
}
|
}
|
},
|
},
|
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v',
|
'file_name' => '/home/alireza/mywork/mpsoc/src_peripheral/ni/ni_master.v',
|
'version' => 40,
|
|
'ip_name' => 'ni_master',
|
'ip_name' => 'ni_master',
|
'system_h' => ' /* NI wb registers addresses
|
'sockets' => {
|
0 : STATUS1_WB_ADDR // status1: {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
|
'ni' => {
|
1 : STATUS2_WB_ADDR // status2: {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
|
'connection_num' => 'single connection',
|
2 : BURST_SIZE_WB_ADDR // The busrt size in words
|
'ni' => {},
|
|
'value' => 1,
|
3 : SEND_DATA_SIZE_WB_ADDR, // The size of data to be sent in byte
|
'0' => {
|
4 : SEND_STRT_WB_ADDR, // The address of data to be sent in byte
|
'name' => 'ni'
|
5 : SEND_DEST_WB_ADDR // The destination router address
|
},
|
6 : SEND_CTRL_WB_ADDR
|
'type' => 'num'
|
|
|
7 : RECEIVE_DATA_SIZE_WB_ADDR // The size of recieved data in byte
|
|
8 : RECEIVE_STRT_WB_ADDR // The address pointer of reciever memory in byte
|
|
9 : RECEIVE_SRC_WB_ADDR // The source router (the router which is sent this packet).
|
|
10 : RECEIVE_CTRL_WB_ADDR // The NI reciever control register
|
|
11 : RECEIVE_MAX_BUFF_SIZ // The receiver\'s allocated buffer size in words. If the packet size is bigger tha the buffer size the rest of will be discarred
|
|
12 : ERROR_FLAGS // errors: {crc_miss_match,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
|
|
|
|
*/
|
|
#define CORID ${CORE_ID}
|
|
#define MAX_X_ADDR ${NX}
|
|
#define MAX_Y_ADDR ${NY}
|
|
|
|
#define Y_ADDR (CORID / MAX_X_ADDR)
|
|
#define X_ADDR (CORID % MAX_X_ADDR)
|
|
|
|
|
|
|
|
#define ${IP}_STATUS1_REG (*((volatile unsigned int *) ($BASE))) //0
|
|
#define ${IP}_STATUS2_REG (*((volatile unsigned int *) ($BASE+4))) //1
|
|
#define ${IP}_BURST_SIZE_REG (*((volatile unsigned int *) ($BASE+8))) //2
|
|
|
|
|
|
#define ${IP}_NUM_VCs ${V}
|
|
|
|
#define ${IP}_SEND_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+12+(v<<6)))) //3
|
|
#define ${IP}_SEND_START_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+16+(v<<6)))) //4
|
|
#define ${IP}_SEND_DEST_REG(v) (*((volatile unsigned int *) ($BASE+20+(v<<6)))) //5
|
|
#define ${IP}_SEND_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+24+(v<<6)))) //6
|
|
|
|
#define ${IP}_RECEIVE_DATA_SIZE_REG(v) (*((volatile unsigned int *) ($BASE+28+(v<<6)))) //7
|
|
#define ${IP}_RECEIVE_STRT_ADDR_REG(v) (*((volatile unsigned int *) ($BASE+32+(v<<6)))) //8
|
|
#define ${IP}_RECEIVE_SRC_REG(v) (*((volatile unsigned int *) ($BASE+36+(v<<6)))) //9
|
|
#define ${IP}_RECEIVE_CTRL_REG(v) (*((volatile unsigned int *) ($BASE+40+(v<<6)))) //10
|
|
#define ${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) (*((volatile unsigned int *) ($BASE+44+(v<<6)))) //11
|
|
#define ${IP}_ERROR_FLAGS_REG(v) (*((volatile unsigned int *) ($BASE+48+(v<<6)))) //12
|
|
|
|
|
|
|
|
// assign status1= {send_vc_is_busy,receive_vc_is_busy,receive_vc_packet_is_saved,receive_vc_got_packet};
|
|
// assign status2= {send_enable_binary,receive_enable_binary,vc_got_error,any_error_isr,got_pck_isr, save_done_isr,send_done_isr,any_error_int_en,got_pck_int_en, save_done_int_en,send_done_int_en};
|
|
|
|
|
|
#define ${IP}_got_packet(v) ((${IP}_STATUS1_REG >> (v)) & 0x1)
|
|
#define ${IP}_packet_is_saved(v) ((${IP}_STATUS1_REG >> (${V}+v)) & 0x1)
|
|
#define ${IP}_receive_is_busy(v) ((${IP}_STATUS1_REG >> (2*${V}+v)) & 0x1)
|
|
#define ${IP}_send_is_busy(v) ((${IP}_STATUS1_REG >> (3*${V}+v)) & 0x1)
|
|
#define ${IP}_got_any_error(v) ((${IP}_STATUS2_REG >> (8+v)) & 0x1)
|
|
|
|
#define SEND_DONE_INT_EN (1<<0)
|
|
#define SAVE_DONE_INT_EN (1<<1)
|
|
#define GOT_PCK_INT_EN (1<<2)
|
|
#define ERRORS_INT_EN (1<<3)
|
|
#define ALL_INT_EN (SEND_DONE_INT_EN | SAVE_DONE_INT_EN | GOT_PCK_INT_EN | ERRORS_INT_EN)
|
|
|
|
#define SEND_DONE_ISR (1<<4)
|
|
#define SAVE_DONE_ISR (1<<5)
|
|
#define GOT_PCK_ISR (1<<6)
|
|
#define ERRORS_ISR (1<<7)
|
|
|
|
|
|
|
|
//errors = {crc_miss_match,illegal_send_req,burst_size_error,send_data_size_error,rcive_buff_ovrflw_err};
|
|
#define BUFF_OVER_FLOW_ERR (1<<0) // This error happens when the receiver allocated buffer size is smaller than the received packet size
|
|
#define SEND_DATA_SIZE_ERR (1<<1) // This error happens when the send data size is not set
|
|
#define BURST_SIZE_ERR (1<<2) // This error happens when the burst size is not set
|
|
#define ILLEGAL_SEND_REQ (1<<3) // This error happens when a new send request is received while the DMA is still busy sending previous packet
|
|
#define CRC_MISS_MATCH (1<<4) // This error happens when the received packet CRC miss match
|
|
|
|
//ack intrrupts functions
|
|
#define ${IP}_ack_send_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN |SEND_DONE_ISR))
|
|
#define ${IP}_ack_save_done_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | SAVE_DONE_ISR))
|
|
#define ${IP}_ack_got_pck_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | GOT_PCK_ISR))
|
|
#define ${IP}_ack_errors_isr() (${IP}_STATUS2_REG &= (ALL_INT_EN | ERRORS_ISR))
|
|
|
|
#define ${IP}_ack_all_isr() (${IP}_STATUS2_REG = ${IP}_STATUS2_REG)
|
|
|
|
|
|
struct SRC_INFOS{
|
|
unsigned char r; // reserved
|
|
unsigned char c; // message class
|
|
unsigned char y; //y address
|
|
unsigned char x ; //x address
|
|
} ;
|
|
|
|
inline struct SRC_INFOS get_src_info(unsigned char v){
|
|
struct SRC_INFOS src_info =*(struct SRC_INFOS *) (&ni_RECEIVE_SRC_REG(v));
|
|
return src_info;
|
|
}
|
|
|
|
/*
|
|
The NI initializing function.
|
|
The burst_size must be <= $MAX_BURST_SIZE
|
|
send_int_en :1: enable the intrrupt when a packet is sent 0 : This intrrupt is disabled
|
|
save_int_en : 1: enable the intrrupt when a recived packet is saved on internal buffer 0 : This intrrupt is disabled
|
|
got_pck_int_en : 1: enable the intrrupt when a packet is recived in NI. 0 : This intrrupt is disabled
|
|
|
|
*/
|
|
void ${IP}_initial (unsigned int burst_size, unsigned char errors_int_en, unsigned char send_int_en, unsigned char save_int_en, unsigned char got_pck_int_en) {
|
|
${IP}_BURST_SIZE_REG = burst_size;
|
|
if(errors_int_en) ${IP}_STATUS2_REG |= ERRORS_INT_EN;
|
|
if(send_int_en) ${IP}_STATUS2_REG |= SEND_DONE_INT_EN;
|
|
if(save_int_en) ${IP}_STATUS2_REG |= SAVE_DONE_INT_EN;
|
|
if(got_pck_int_en) ${IP}_STATUS2_REG |= GOT_PCK_INT_EN;
|
|
}
|
|
|
|
/*
|
|
The NI message sent function:
|
|
v: virtual channel number which this packet should be sent to
|
|
class_num: message class number. Diffrent message classes can be sent via isolated network resources to avoid protocol deadlock
|
|
data_start_addr : The address pointer to the start location of the packet to be sent in the memory
|
|
data_size: the message data size in words
|
|
dest_x: the x address of destination core
|
|
dest_y: the y address of destination core
|
|
|
|
*/
|
|
|
|
void ${IP}_transfer (unsigned int v, unsigned int class_num, unsigned int data_start_addr, unsigned int data_size, unsigned int dest_x,unsigned int dest_y){
|
|
while (${IP}_send_is_busy(v)); // wait until VC is busy sending previous packet
|
|
|
|
${IP}_SEND_DATA_SIZE_REG(v) = data_size;
|
|
${IP}_SEND_START_ADDR_REG(v) = data_start_addr;
|
|
${IP}_SEND_DEST_REG(v) = dest_x | (dest_y<<4)| (class_num<<8) ;
|
|
|
|
}
|
}
|
|
},
|
/*
|
'ports_order' => [
|
The NI message receiver function:
|
'reset',
|
v: virtual channel number of the received packet
|
'clk',
|
data_start_addr : The address pointer to the start location of the memory where the newly arrived packet must be stored by NI in.
|
'current_e_addr',
|
max_buffer_size : The allocated receive-memory buffer size in words.
|
'current_r_addr',
|
*/
|
'flit_out',
|
|
'flit_out_wr',
|
void ${IP}_receive (unsigned int v, unsigned int data_start_addr, unsigned int max_buffer_size){
|
'credit_in',
|
while (${IP}_receive_is_busy(v)); // wait until VC is busy saving previous packet
|
'flit_in',
|
|
'flit_in_wr',
|
${IP}_RECEIVE_STRT_ADDR_REG(v) = data_start_addr;
|
'credit_out',
|
${IP}_RECEIVE_MAX_BUFF_SIZ_REG(v) = max_buffer_size;
|
's_dat_i',
|
${IP}_RECEIVE_CTRL_REG(v) = 1;
|
's_sel_i',
|
|
's_addr_i',
|
|
's_cti_i',
|
}',
|
's_stb_i',
|
|
's_cyc_i',
|
|
's_we_i',
|
|
's_dat_o',
|
|
's_ack_o',
|
|
'm_send_sel_o',
|
|
'm_send_addr_o',
|
|
'm_send_cti_o',
|
|
'm_send_stb_o',
|
|
'm_send_cyc_o',
|
|
'm_send_we_o',
|
|
'm_send_dat_i',
|
|
'm_send_ack_i',
|
|
'm_receive_sel_o',
|
|
'm_receive_dat_o',
|
|
'm_receive_addr_o',
|
|
'm_receive_cti_o',
|
|
'm_receive_stb_o',
|
|
'm_receive_cyc_o',
|
|
'm_receive_we_o',
|
|
'm_receive_ack_i',
|
|
'irq'
|
|
],
|
'description' => '',
|
'description' => '',
|
|
'unused' => {
|
|
'plug:wb_master[1]' => [
|
|
'tag_o',
|
|
'dat_i',
|
|
'bte_o',
|
|
'err_i',
|
|
'rty_i'
|
|
],
|
|
'plug:wb_master[0]' => [
|
|
'tag_o',
|
|
'bte_o',
|
|
'err_i',
|
|
'dat_o',
|
|
'rty_i'
|
|
],
|
|
'plug:wb_slave[0]' => [
|
|
'tag_i',
|
|
'err_o',
|
|
'rty_o',
|
|
'bte_i'
|
|
]
|
|
},
|
'gui_status' => {
|
'gui_status' => {
|
'timeout' => 0,
|
'status' => 'ideal',
|
'status' => 'ideal'
|
'timeout' => 0
|
}
|
},
|
|
'hdl_files' => [
|
|
'/mpsoc/src_noc/arbiter.v',
|
|
'/mpsoc/src_noc/flit_buffer.v',
|
|
'/mpsoc/src_noc/input_ports.v',
|
|
'/mpsoc/src_noc/main_comp.v',
|
|
'/mpsoc/src_noc/route_mesh.v',
|
|
'/mpsoc/src_noc/route_torus.v',
|
|
'/mpsoc/src_noc/routing.v',
|
|
'/mpsoc/src_peripheral/ni/ni_vc_dma.v',
|
|
'/mpsoc/src_peripheral/ni/ni_vc_wb_slave_regs.v',
|
|
'/mpsoc/src_peripheral/ni/ni_master.v',
|
|
'/mpsoc/src_peripheral/ni/ni_crc32.v',
|
|
'/mpsoc/src_noc/topology_localparam.v'
|
|
],
|
|
'module_name' => 'ni_master',
|
|
'version' => 60
|
}, 'ip_gen' );
|
}, 'ip_gen' );
|
