Line 1... |
Line 1... |
#######################################################################
|
#######################################################################
|
## File: Or1200.IP
|
## File: Or1200.IP
|
##
|
##
|
## Copyright (C) 2014-2016 Alireza Monemi
|
## Copyright (C) 2014-2019 Alireza Monemi
|
##
|
##
|
## This file is part of ProNoC 1.7.0
|
## This file is part of ProNoC 1.9.1
|
##
|
##
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
################################################################################
|
################################################################################
|
|
|
$or1200 = bless( {
|
$ipgen = bless( {
|
'system_h' => ' #include "or1200/system.h"
|
'ip_name' => 'Or1200',
|
|
'parameters_order' => [
|
|
'dw',
|
inline void nop (){
|
'aw',
|
__asm__("l.nop 1");
|
'ppic_ints',
|
}',
|
'boot_adr',
|
'category' => 'Processor',
|
'Data_cashe_size',
|
'sw_files' => [
|
'Instruction_cashe_size',
|
'/mpsoc/src_processor/or1200/sw/Makefile',
|
'Data_cashe_enable',
|
'/mpsoc/src_processor/or1200/sw/or1200',
|
'Instruction_cashe_enable',
|
'/mpsoc/src_processor/or1200/sw/link.ld',
|
'Data_MMU_enable',
|
'/mpsoc/src_processor/or1200/sw/define_printf.h',
|
'Instruction_MMU_enable',
|
'/mpsoc/src_processor/src_lib/simple-printf'
|
'implementation_addc',
|
|
'implement_sub',
|
|
'implement_cy',
|
|
'implement_0v',
|
|
'implement_OVE',
|
|
'implement_alu_rotate',
|
|
'implement_alu_compare',
|
|
'implement_alu_ext',
|
|
'multiplier_type',
|
|
'divider_type'
|
],
|
],
|
'file_name' => '/home/alireza/mywork/mpsoc/src_processor/or1200/verilog/or1200.v',
|
'version' => 34,
|
'hdl_files' => [
|
'hdl_files' => [
|
'/mpsoc/src_processor/or1200/verilog/or1200.v',
|
'/mpsoc/src_processor/or1200/verilog/or1200.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_alu.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_amultp2_32x32.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_cfgr.v',
|
Line 103... |
Line 112... |
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_wb_biu.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_wbmux.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
|
'/mpsoc/src_processor/or1200/verilog/src/or1200_xcv_ram32x8d.v',
|
'/mpsoc/src_processor/or1200/verilog/src/timescale.v'
|
'/mpsoc/src_processor/or1200/verilog/src/timescale.v'
|
],
|
],
|
'ip_name' => 'Or1200',
|
'gen_hw_files' => [
|
'plugs' => {
|
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
|
'reset' => {
|
],
|
'type' => 'num',
|
|
'value' => 1,
|
|
'0' => {
|
|
'name' => 'reset'
|
|
}
|
|
},
|
|
'enable' => {
|
|
'0' => {
|
|
'name' => 'enable'
|
|
},
|
|
'enable' => {},
|
|
'value' => 1,
|
|
'type' => 'num'
|
|
},
|
|
'wb_master' => {
|
|
'0' => {
|
|
'name' => 'iwb'
|
|
},
|
|
'type' => 'num',
|
|
'value' => 2,
|
|
'1' => {
|
|
'name' => 'dwb'
|
|
}
|
|
},
|
|
'clk' => {
|
|
'0' => {
|
|
'name' => 'clk'
|
|
},
|
|
'type' => 'num',
|
|
'value' => 1
|
|
}
|
|
},
|
|
'ports' => {
|
'ports' => {
|
'reset' => {
|
'iwb_stb_o' => {
|
'intfc_port' => 'reset_i',
|
'intfc_port' => 'stb_o',
|
'intfc_name' => 'plug:reset[0]',
|
|
'type' => 'input'
|
|
},
|
|
'dwb_sel_o' => {
|
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '3:0',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'sel_o',
|
'range' => ''
|
'intfc_name' => 'plug:wb_master[1]'
|
|
},
|
},
|
'dwb_cti_o' => {
|
'en_i' => {
|
'intfc_port' => 'cti_o',
|
'intfc_name' => 'plug:enable[0]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'input',
|
'type' => 'output',
|
'range' => '',
|
'range' => '2:0'
|
'intfc_port' => 'enable_i'
|
},
|
},
|
'dwb_bte_o' => {
|
'iwb_bte_o' => {
|
'type' => 'output',
|
|
'range' => '1:0',
|
|
'intfc_port' => 'bte_o',
|
'intfc_port' => 'bte_o',
|
'intfc_name' => 'plug:wb_master[1]'
|
|
},
|
|
'iwb_cyc_o' => {
|
|
'intfc_port' => 'cyc_o',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'output',
|
'type' => 'output',
|
'range' => ''
|
'range' => '1:0'
|
},
|
},
|
'dwb_adr_o' => {
|
'dwb_dat_o' => {
|
'intfc_port' => 'adr_o',
|
'intfc_port' => 'dat_o',
|
|
'range' => 'dw-1:0',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => 'aw-1:0',
|
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'iwb_err_i' => {
|
'iwb_err_i' => {
|
'intfc_port' => 'err_i',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'range' => '',
|
'range' => '',
|
|
'type' => 'input',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'err_i'
|
|
},
|
|
'reset' => {
|
|
'intfc_port' => 'reset_i',
|
|
'intfc_name' => 'plug:reset[0]',
|
'type' => 'input'
|
'type' => 'input'
|
},
|
},
|
'dwb_we_o' => {
|
'dwb_stb_o' => {
|
|
'intfc_port' => 'stb_o',
|
'range' => '',
|
'range' => '',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_port' => 'we_o'
|
|
},
|
|
'dwb_rty_i' => {
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'intfc_port' => 'rty_i',
|
|
'type' => 'input',
|
|
'range' => ''
|
|
},
|
|
'dwb_dat_o' => {
|
|
'intfc_port' => 'dat_o',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'type' => 'output',
|
|
'range' => 'dw-1:0'
|
|
},
|
},
|
'iwb_dat_o' => {
|
'iwb_dat_o' => {
|
'intfc_port' => 'dat_o',
|
'intfc_port' => 'dat_o',
|
|
'range' => 'dw-1:0',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'output',
|
'type' => 'output'
|
'range' => 'dw-1:0'
|
|
},
|
},
|
'iwb_rty_i' => {
|
'iwb_rty_i' => {
|
'intfc_port' => 'rty_i',
|
'intfc_port' => 'rty_i',
|
'intfc_name' => 'plug:wb_master[0]',
|
'range' => '',
|
'type' => 'input',
|
'type' => 'input',
|
'range' => ''
|
'intfc_name' => 'plug:wb_master[0]'
|
},
|
},
|
'iwb_sel_o' => {
|
'dwb_we_o' => {
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'we_o',
|
'intfc_port' => 'sel_o',
|
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '3:0'
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'range' => ''
|
},
|
},
|
'clk' => {
|
'iwb_dat_i' => {
|
'range' => '',
|
'range' => 'dw-1:0',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'clk_i',
|
'intfc_port' => 'dat_i'
|
'intfc_name' => 'plug:clk[0]'
|
|
},
|
},
|
'en_i' => {
|
'iwb_we_o' => {
|
'intfc_port' => 'enable_i',
|
'intfc_port' => 'we_o',
|
'intfc_name' => 'plug:enable[0]',
|
'type' => 'output',
|
'type' => 'input',
|
'intfc_name' => 'plug:wb_master[0]',
|
'range' => ''
|
'range' => ''
|
},
|
},
|
'dwb_cyc_o' => {
|
'dwb_cyc_o' => {
|
'type' => 'output',
|
|
'range' => '',
|
|
'intfc_port' => 'cyc_o',
|
'intfc_port' => 'cyc_o',
|
'intfc_name' => 'plug:wb_master[1]'
|
'range' => '',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'type' => 'output'
|
},
|
},
|
'iwb_dat_i' => {
|
'dwb_cti_o' => {
|
'range' => 'dw-1:0',
|
'intfc_port' => 'cti_o',
|
'type' => 'input',
|
'range' => '2:0',
|
'intfc_port' => 'dat_i',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[0]'
|
'type' => 'output'
|
},
|
},
|
'iwb_stb_o' => {
|
'iwb_cyc_o' => {
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'cyc_o'
|
'intfc_port' => 'stb_o'
|
|
},
|
},
|
'dwb_ack_i' => {
|
'dwb_err_i' => {
|
'type' => 'input',
|
'intfc_port' => 'err_i',
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_port' => 'ack_i'
|
'type' => 'input'
|
},
|
},
|
'dwb_dat_i' => {
|
'pic_ints_i' => {
|
|
'intfc_port' => 'int_i',
|
|
'range' => 'ppic_ints-1:0',
|
|
'intfc_name' => 'socket:interrupt_peripheral[array]',
|
|
'type' => 'input'
|
|
},
|
|
'iwb_sel_o' => {
|
|
'intfc_port' => 'sel_o',
|
|
'range' => '3:0',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'type' => 'output'
|
|
},
|
|
'dwb_rty_i' => {
|
|
'intfc_port' => 'rty_i',
|
'type' => 'input',
|
'type' => 'input',
|
'range' => 'dw-1:0',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_port' => 'dat_i'
|
'range' => ''
|
|
},
|
|
'dwb_adr_o' => {
|
|
'intfc_port' => 'adr_o',
|
|
'range' => 'aw-1:0',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'type' => 'output'
|
},
|
},
|
'iwb_cti_o' => {
|
'iwb_cti_o' => {
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'cti_o',
|
'intfc_port' => 'cti_o',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '2:0'
|
'range' => '2:0'
|
},
|
},
|
'iwb_we_o' => {
|
'dwb_sel_o' => {
|
'intfc_port' => 'we_o',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => '',
|
'range' => '3:0',
|
'type' => 'output'
|
'intfc_port' => 'sel_o'
|
},
|
},
|
'iwb_adr_o' => {
|
'iwb_adr_o' => {
|
'range' => 'aw-1:0',
|
'range' => 'aw-1:0',
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'type' => 'output',
|
'intfc_port' => 'adr_o'
|
'intfc_port' => 'adr_o'
|
},
|
},
|
'dwb_err_i' => {
|
'dwb_bte_o' => {
|
'range' => '',
|
|
'type' => 'input',
|
|
'intfc_port' => 'err_i',
|
|
'intfc_name' => 'plug:wb_master[1]'
|
|
},
|
|
'iwb_bte_o' => {
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'bte_o',
|
'intfc_port' => 'bte_o',
|
'type' => 'output',
|
'range' => '1:0',
|
'range' => '1:0'
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'type' => 'output'
|
},
|
},
|
'dwb_stb_o' => {
|
'dwb_dat_i' => {
|
'intfc_port' => 'stb_o',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'output',
|
'type' => 'input',
|
'range' => ''
|
'range' => 'dw-1:0',
|
|
'intfc_port' => 'dat_i'
|
},
|
},
|
'iwb_ack_i' => {
|
'iwb_ack_i' => {
|
'range' => '',
|
'range' => '',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'ack_i',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]'
|
'intfc_port' => 'ack_i'
|
},
|
|
'pic_ints_i' => {
|
|
'intfc_port' => 'int_i',
|
|
'intfc_name' => 'socket:interrupt_peripheral[array]',
|
|
'range' => 'ppic_ints-1:0',
|
|
'type' => 'input'
|
|
}
|
|
},
|
},
|
'parameters_order' => [
|
'clk' => {
|
'dw',
|
'intfc_port' => 'clk_i',
|
'aw',
|
'range' => '',
|
'ppic_ints',
|
'type' => 'input',
|
'boot_adr',
|
'intfc_name' => 'plug:clk[0]'
|
'Data_cashe_size',
|
},
|
'Instruction_cashe_size',
|
'dwb_ack_i' => {
|
'Data_cashe_enable',
|
'range' => '',
|
'Instruction_cashe_enable',
|
'intfc_name' => 'plug:wb_master[1]',
|
'Data_MMU_enable',
|
'type' => 'input',
|
'Instruction_MMU_enable',
|
'intfc_port' => 'ack_i'
|
'implementation_addc',
|
}
|
'implement_sub',
|
},
|
'implement_cy',
|
'system_h' => ' #include "or1200/system.h"
|
'implement_0v',
|
|
'implement_OVE',
|
|
'implement_alu_rotate',
|
static inline void nop (){
|
'implement_alu_compare',
|
__asm__("l.nop 1");
|
'implement_alu_ext',
|
}',
|
'multiplier_type',
|
'plugs' => {
|
'divider_type'
|
'reset' => {
|
|
'0' => {
|
|
'name' => 'reset'
|
|
},
|
|
'type' => 'num',
|
|
'value' => 1
|
|
},
|
|
'clk' => {
|
|
'value' => 1,
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'clk'
|
|
}
|
|
},
|
|
'wb_master' => {
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'iwb'
|
|
},
|
|
'1' => {
|
|
'name' => 'dwb'
|
|
},
|
|
'value' => 2
|
|
},
|
|
'enable' => {
|
|
'0' => {
|
|
'name' => 'enable'
|
|
},
|
|
'type' => 'num',
|
|
'value' => 1,
|
|
'enable' => {}
|
|
}
|
|
},
|
|
'ports_order' => [
|
|
'clk',
|
|
'reset',
|
|
'en_i',
|
|
'pic_ints_i',
|
|
'iwb_ack_i',
|
|
'iwb_err_i',
|
|
'iwb_rty_i',
|
|
'iwb_dat_i',
|
|
'iwb_cyc_o',
|
|
'iwb_adr_o',
|
|
'iwb_stb_o',
|
|
'iwb_we_o',
|
|
'iwb_sel_o',
|
|
'iwb_dat_o',
|
|
'iwb_cti_o',
|
|
'iwb_bte_o',
|
|
'dwb_ack_i',
|
|
'dwb_err_i',
|
|
'dwb_rty_i',
|
|
'dwb_dat_i',
|
|
'dwb_cyc_o',
|
|
'dwb_adr_o',
|
|
'dwb_stb_o',
|
|
'dwb_we_o',
|
|
'dwb_sel_o',
|
|
'dwb_dat_o',
|
|
'dwb_cti_o',
|
|
'dwb_bte_o'
|
],
|
],
|
|
'modules' => {
|
|
'or1200' => {}
|
|
},
|
'unused' => {
|
'unused' => {
|
'plug:wb_master[1]' => [
|
'plug:wb_master[0]' => [
|
'tag_o'
|
'tag_o'
|
],
|
],
|
'plug:wb_master[0]' => [
|
'plug:wb_master[1]' => [
|
'tag_o'
|
'tag_o'
|
]
|
]
|
},
|
},
|
'parameters' => {
|
'parameters' => {
|
'implement_0v' => {
|
|
'content' => '0V,NO_0V',
|
|
'redefine_param' => 0,
|
|
'global_param' => 'Don\'t include',
|
|
'info' => 'Implement carry bit SR[OV]
|
|
Compiler doesn\'t use this, but other code may like to.',
|
|
'default' => '0V',
|
|
'type' => 'Combo-box'
|
|
},
|
|
'implement_alu_ext' => {
|
'implement_alu_ext' => {
|
'global_param' => 'Don\'t include',
|
|
'content' => 'EXT,NO_EXT',
|
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'type' => 'Combo-box',
|
|
'info' => 'Implement l.extXs and l.extXz instructions',
|
'info' => 'Implement l.extXs and l.extXz instructions',
|
'default' => 'NO_EXT'
|
'default' => 'NO_EXT',
|
},
|
|
'Data_MMU_enable' => {
|
|
'content' => 'NO,YES',
|
|
'redefine_param' => 0,
|
|
'global_param' => 'Don\'t include',
|
|
'default' => 'YES',
|
|
'info' => undef,
|
|
'type' => 'Combo-box'
|
|
},
|
|
'aw' => {
|
|
'type' => 'Fixed',
|
|
'info' => 'Parameter',
|
|
'default' => '32',
|
|
'global_param' => 'Parameter',
|
|
'content' => '',
|
|
'redefine_param' => 1
|
|
},
|
|
'Data_cashe_enable' => {
|
|
'info' => undef,
|
|
'default' => 'YES',
|
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'redefine_param' => 0,
|
|
'content' => 'NO,YES',
|
|
'global_param' => 'Don\'t include'
|
|
},
|
|
'implement_OVE' => {
|
|
'redefine_param' => 0,
|
|
'content' => 'OVE,NO_OVE',
|
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
'info' => 'Implement carry bit SR[OVE]
|
'content' => 'EXT,NO_EXT'
|
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
|
|
'default' => 'NO_OVE',
|
|
'type' => 'Combo-box'
|
|
},
|
},
|
'implementation_addc' => {
|
'multiplier_type' => {
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
'content' => 'ADDC,NO_ADDC',
|
'content' => 'SERIAL,PARALLEL',
|
|
'default' => 'SERIAL',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'type' => 'Combo-box',
|
'info' => undef,
|
'default' => 'ADDC',
|
'type' => 'Combo-box'
|
'info' => 'Implement l.addc/l.addic instructions
|
|
By default implementation of l.addc/l.addic instructions is enabled in case you need them.
|
|
If you don\'t use them, then disable implementation to save area.'
|
|
},
|
},
|
'implement_sub' => {
|
'Instruction_cashe_size' => {
|
|
'default' => '8K',
|
|
'redefine_param' => 0,
|
|
'info' => 'Instruction Cashe Size in B',
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'default' => 'SUB',
|
|
'info' => 'Implement l.sub instruction
|
|
By default implementation of l.sub instructions is enabled to be compliant with the simulator.
|
|
If you don\'t use carry bit, then disable implementation to save area.',
|
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
'content' => 'SUB,NO_SUB',
|
'content' => '512,4K,8K,16K,32K'
|
'redefine_param' => 0
|
|
},
|
},
|
'divider_type' => {
|
'divider_type' => {
|
'type' => 'Combo-box',
|
|
'default' => 'SERIAL',
|
|
'info' => undef,
|
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
|
'content' => 'SERIAL,PARALLEL',
|
|
'info' => undef,
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => 'SERIAL,PARALLEL'
|
'default' => 'SERIAL',
|
|
'type' => 'Combo-box'
|
},
|
},
|
'Instruction_MMU_enable' => {
|
'dw' => {
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Localparam',
|
'content' => 'NO,YES',
|
'content' => '',
|
|
'default' => '32',
|
|
'info' => 'Parameter',
|
|
'redefine_param' => 1,
|
|
'type' => 'Fixed'
|
|
},
|
|
'implement_alu_compare' => {
|
|
'default' => '2',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
|
'info' => 'Type of ALU compare to implement
|
|
Try to find which synthesizes with most efficient logic use or highest speed.',
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'default' => 'YES',
|
'global_param' => 'Don\'t include',
|
'info' => undef
|
'content' => '1,2,3'
|
},
|
},
|
'implement_alu_rotate' => {
|
'implement_alu_rotate' => {
|
'global_param' => 'Don\'t include',
|
|
'redefine_param' => 0,
|
|
'content' => 'ROTATE,NO_ROTATE',
|
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
|
'default' => 'ROTATE',
|
'info' => 'Implement rotate in the ALU
|
'info' => 'Implement rotate in the ALU
|
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
|
At the time of writing this, or32 C/C++ compiler doesn\'t generate rotate instructions. However or32 assembler can assemble code that uses rotate insn.
|
This means that rotate instructions must be used manually inserted.
|
This means that rotate instructions must be used manually inserted.
|
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
|
By default implementation of rotate is disabled to save area and increase is disabled to save area and increase clock frequency.',
|
'default' => 'ROTATE'
|
'redefine_param' => 0,
|
|
'content' => 'ROTATE,NO_ROTATE',
|
|
'global_param' => 'Don\'t include'
|
},
|
},
|
'multiplier_type' => {
|
'implement_OVE' => {
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
|
'content' => 'OVE,NO_OVE',
|
|
'default' => 'NO_OVE',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => 'SERIAL,PARALLEL',
|
'info' => 'Implement carry bit SR[OVE]
|
|
Overflow interrupt indicator. When enabled, SR[OV] flag does not remain asserted after exception.',
|
|
'type' => 'Combo-box'
|
|
},
|
|
'Data_cashe_enable' => {
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
|
'default' => 'YES',
|
'info' => undef,
|
'info' => undef,
|
'default' => 'SERIAL'
|
'redefine_param' => 0,
|
|
'content' => 'NO,YES',
|
|
'global_param' => 'Don\'t include'
|
},
|
},
|
'boot_adr' => {
|
'ppic_ints' => {
|
'content' => '',
|
'default' => '20',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Parameter',
|
'info' => 'Number of interrupts',
|
'info' => 'Parameter',
|
'type' => 'Spin-button',
|
'default' => '32\'h00000100',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed'
|
'content' => '3,31,1'
|
},
|
},
|
'Instruction_cashe_enable' => {
|
'Instruction_cashe_enable' => {
|
|
'info' => undef,
|
|
'redefine_param' => 0,
|
|
'default' => 'YES',
|
|
'type' => 'Combo-box',
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
|
'content' => 'NO,YES'
|
|
},
|
|
'implementation_addc' => {
|
|
'default' => 'ADDC',
|
|
'info' => 'Implement l.addc/l.addic instructions
|
|
By default implementation of l.addc/l.addic instructions is enabled in case you need them.
|
|
If you don\'t use them, then disable implementation to save area.',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => 'NO,YES',
|
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'info' => undef,
|
'global_param' => 'Don\'t include',
|
'default' => 'YES'
|
'content' => 'ADDC,NO_ADDC'
|
},
|
},
|
'ppic_ints' => {
|
'aw' => {
|
'content' => '3,31,1',
|
'content' => '',
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed',
|
|
'info' => 'Parameter',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Parameter',
|
'default' => '32'
|
'info' => 'Number of interrupts',
|
},
|
'default' => '20',
|
'implement_sub' => {
|
'type' => 'Spin-button'
|
'content' => 'SUB,NO_SUB',
|
|
'global_param' => 'Don\'t include',
|
|
'type' => 'Combo-box',
|
|
'info' => 'Implement l.sub instruction
|
|
By default implementation of l.sub instructions is enabled to be compliant with the simulator.
|
|
If you don\'t use carry bit, then disable implementation to save area.',
|
|
'redefine_param' => 0,
|
|
'default' => 'SUB'
|
},
|
},
|
'Data_cashe_size' => {
|
'Data_cashe_size' => {
|
|
'global_param' => 'Don\'t include',
|
'content' => '512,4K,8K,16K,32K',
|
'content' => '512,4K,8K,16K,32K',
|
|
'default' => '8K',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'global_param' => 'Don\'t include',
|
|
'info' => 'Data Cashe Size in B',
|
'info' => 'Data Cashe Size in B',
|
'default' => '8K',
|
|
'type' => 'Combo-box'
|
'type' => 'Combo-box'
|
},
|
},
|
'Instruction_cashe_size' => {
|
'Data_MMU_enable' => {
|
'default' => '8K',
|
'default' => 'YES',
|
'info' => 'Instruction Cashe Size in B',
|
|
'type' => 'Combo-box',
|
|
'content' => '512,4K,8K,16K,32K',
|
|
'redefine_param' => 0,
|
|
'global_param' => 'Don\'t include'
|
|
},
|
|
'implement_alu_compare' => {
|
|
'global_param' => 'Don\'t include',
|
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => '1,2,3',
|
'info' => undef,
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'default' => '2',
|
'global_param' => 'Don\'t include',
|
'info' => 'Type of ALU compare to implement
|
'content' => 'NO,YES'
|
Try to find which synthesizes with most efficient logic use or highest speed.'
|
|
},
|
},
|
'dw' => {
|
'boot_adr' => {
|
'default' => '32',
|
|
'info' => 'Parameter',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
|
'default' => '32\'h00000100',
|
|
'info' => 'Parameter',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'content' => '',
|
'content' => '',
|
'global_param' => 'Parameter'
|
'global_param' => 'Localparam'
|
|
},
|
|
'implement_0v' => {
|
|
'content' => '0V,NO_0V',
|
|
'global_param' => 'Don\'t include',
|
|
'type' => 'Combo-box',
|
|
'default' => '0V',
|
|
'redefine_param' => 0,
|
|
'info' => 'Implement carry bit SR[OV]
|
|
Compiler doesn\'t use this, but other code may like to.'
|
},
|
},
|
'implement_cy' => {
|
'implement_cy' => {
|
|
'content' => 'CY,NO_CY',
|
|
'global_param' => 'Don\'t include',
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'info' => 'Implement carry bit SR[CY]
|
'info' => 'Implement carry bit SR[CY]
|
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
|
By default implementation of SR[CY] is enabled to be compliant with the simulator. However SR[CY] is explicitly only used by l.addc/l.addic/l.sub instructions and if these three insns are not implemented there is not much point having SR[CY].',
|
'default' => 'CY',
|
'redefine_param' => 0,
|
|
'default' => 'CY'
|
|
},
|
|
'Instruction_MMU_enable' => {
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
|
'content' => 'NO,YES',
|
'redefine_param' => 0,
|
'redefine_param' => 0,
|
'content' => 'CY,NO_CY'
|
'info' => undef,
|
|
'default' => 'YES',
|
|
'type' => 'Combo-box'
|
}
|
}
|
},
|
},
|
'modules' => {
|
'gui_status' => {
|
'or1200' => {}
|
'status' => 'ideal',
|
|
'timeout' => 0
|
},
|
},
|
'sockets' => {
|
'sockets' => {
|
'interrupt_peripheral' => {
|
'interrupt_peripheral' => {
|
'type' => 'param',
|
|
'value' => 'ppic_ints',
|
|
'connection_num' => 'single connection',
|
'connection_num' => 'single connection',
|
|
'value' => 'ppic_ints',
|
'0' => {
|
'0' => {
|
'name' => 'interrupt'
|
'name' => 'interrupt'
|
}
|
},
|
|
'type' => 'param'
|
}
|
}
|
},
|
},
|
'ports_order' => [
|
'sw_files' => [
|
'clk',
|
'/mpsoc/src_processor/or1200/sw/Makefile',
|
'reset',
|
'/mpsoc/src_processor/or1200/sw/or1200',
|
'en_i',
|
'/mpsoc/src_processor/or1200/sw/link.ld',
|
'pic_ints_i',
|
'/mpsoc/src_processor/or1200/sw/define_printf.h',
|
'iwb_ack_i',
|
'/mpsoc/src_processor/src_lib/simple-printf'
|
'iwb_err_i',
|
|
'iwb_rty_i',
|
|
'iwb_dat_i',
|
|
'iwb_cyc_o',
|
|
'iwb_adr_o',
|
|
'iwb_stb_o',
|
|
'iwb_we_o',
|
|
'iwb_sel_o',
|
|
'iwb_dat_o',
|
|
'iwb_cti_o',
|
|
'iwb_bte_o',
|
|
'dwb_ack_i',
|
|
'dwb_err_i',
|
|
'dwb_rty_i',
|
|
'dwb_dat_i',
|
|
'dwb_cyc_o',
|
|
'dwb_adr_o',
|
|
'dwb_stb_o',
|
|
'dwb_we_o',
|
|
'dwb_sel_o',
|
|
'dwb_dat_o',
|
|
'dwb_cti_o',
|
|
'dwb_bte_o'
|
|
],
|
],
|
|
'category' => 'Processor',
|
'module_name' => 'or1200',
|
'module_name' => 'or1200',
|
'gen_hw_files' => [
|
'file_name' => 'mpsoc/src_processor/or1200/verilog/or1200.v'
|
'/mpsoc/src_processor/or1200/verilog/or1200_definesfrename_sep_tlib/or1200_defines.v'
|
|
],
|
|
'gui_status' => {
|
|
'timeout' => 0,
|
|
'status' => 'ideal'
|
|
},
|
|
'version' => 32
|
|
}, 'ip_gen' );
|
}, 'ip_gen' );
|