| Line 1... |
Line 1... |
#######################################################################
|
#######################################################################
|
## File: aeMB.IP
|
## File: aeMB.IP
|
##
|
##
|
## Copyright (C) 2014-2016 Alireza Monemi
|
## Copyright (C) 2014-2019 Alireza Monemi
|
##
|
##
|
## This file is part of ProNoC 1.7.0
|
## This file is part of ProNoC 1.9.1
|
##
|
##
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
## MAY CAUSE UNEXPECTED BEHAVIOR.
|
################################################################################
|
################################################################################
|
|
|
$ipgen = bless( {
|
$ipgen = bless( {
|
'unused' => undef,
|
'plugs' => {
|
|
'enable' => {
|
|
'value' => 1,
|
|
'0' => {
|
|
'name' => 'enable'
|
|
},
|
|
'enable' => {},
|
|
'type' => 'num'
|
|
},
|
|
'wb_master' => {
|
|
'wb_master' => {},
|
|
'value' => 2,
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'iwb'
|
|
},
|
|
'1' => {
|
|
'name' => 'dwb'
|
|
}
|
|
},
|
|
'clk' => {
|
|
'clk' => {},
|
|
'0' => {
|
|
'name' => 'clk'
|
|
},
|
|
'type' => 'num',
|
|
'value' => 1
|
|
},
|
|
'reset' => {
|
|
'reset' => {},
|
|
'value' => 1,
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'reset'
|
|
}
|
|
}
|
|
},
|
|
'sockets' => {
|
|
'interrupt_cpu' => {
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'interrupt_cpu'
|
|
},
|
|
'connection_num' => 'single connection',
|
|
'value' => 1
|
|
}
|
|
},
|
|
'gen_sw_files_ticked' => [],
|
|
'system_h' => '
|
|
#include "aemb/core.hh"
|
|
|
|
static inline void nop (void) {
|
|
asm volatile ("nop");
|
|
}
|
|
|
|
void general_int_main( void ) __attribute__ ((interrupt_handler)); // general_int_main() is defined by interrupt controller
|
|
void aemb_enable_interrupt (void);
|
|
void exit (int);
|
|
|
|
#define general_cpu_int_en aemb_enable_interrupt
|
|
|
|
',
|
'parameters' => {
|
'parameters' => {
|
'AEMB_DWB' => {
|
'AEMB_BSF' => {
|
'redefine_param' => 1,
|
|
'info' => undef,
|
|
'default' => ' 32',
|
|
'content' => '',
|
'content' => '',
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed'
|
'type' => 'Fixed',
|
|
'info' => undef,
|
|
'redefine_param' => 1,
|
|
'default' => ' 1'
|
},
|
},
|
'AEMB_BSF' => {
|
'AEMB_ICH' => {
|
'default' => ' 1',
|
'global_param' => 'Localparam',
|
'content' => '',
|
'content' => '',
|
|
'default' => ' 11',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'info' => undef,
|
'info' => undef,
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed'
|
'type' => 'Fixed'
|
},
|
},
|
'AEMB_IWB' => {
|
'AEMB_IDX' => {
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'content' => '',
|
'info' => undef,
|
'default' => ' 32',
|
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'info' => undef
|
'default' => ' 6',
|
},
|
|
'AEMB_XWB' => {
|
|
'type' => 'Fixed',
|
|
'global_param' => 'Localparam',
|
|
'content' => '',
|
'content' => '',
|
'default' => ' 7',
|
'global_param' => 'Localparam'
|
'info' => undef,
|
|
'redefine_param' => 1
|
|
},
|
},
|
'HEAP_SIZE' => {
|
'AEMB_IWB' => {
|
'info' => undef,
|
'info' => undef,
|
'redefine_param' => 0,
|
'type' => 'Fixed',
|
|
'redefine_param' => 1,
|
|
'default' => ' 32',
|
'content' => '',
|
'content' => '',
|
'default' => '0x400',
|
'global_param' => 'Localparam'
|
'type' => 'Entry',
|
|
'global_param' => 'Don\'t include'
|
|
},
|
},
|
'AEMB_MUL' => {
|
'AEMB_DWB' => {
|
'default' => ' 1',
|
'global_param' => 'Localparam',
|
'content' => '',
|
'content' => '',
|
'info' => undef,
|
'default' => ' 32',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Localparam'
|
'info' => undef
|
},
|
},
|
'AEMB_IDX' => {
|
'AEMB_MUL' => {
|
'info' => undef,
|
|
'redefine_param' => 1,
|
|
'default' => ' 6',
|
|
'content' => '',
|
'content' => '',
|
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'global_param' => 'Localparam'
|
'info' => undef,
|
|
'default' => ' 1',
|
|
'redefine_param' => 1
|
},
|
},
|
'AEMB_ICH' => {
|
'STACK_SIZE' => {
|
|
'content' => '',
|
|
'global_param' => 'Don\'t include',
|
|
'type' => 'Entry',
|
|
'info' => 'The stack size in hex',
|
|
'redefine_param' => 0,
|
|
'default' => '0x400'
|
|
},
|
|
'AEMB_XWB' => {
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'type' => 'Fixed',
|
|
'content' => '',
|
'content' => '',
|
'default' => ' 11',
|
'default' => ' 7',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
|
'type' => 'Fixed',
|
'info' => undef
|
'info' => undef
|
},
|
},
|
'STACK_SIZE' => {
|
'HEAP_SIZE' => {
|
'type' => 'Entry',
|
|
'global_param' => 'Don\'t include',
|
'global_param' => 'Don\'t include',
|
'default' => '0x400',
|
|
'content' => '',
|
'content' => '',
|
'info' => 'The stack size in hex',
|
'default' => '0x400',
|
'redefine_param' => 0
|
'redefine_param' => 0,
|
|
'type' => 'Entry',
|
|
'info' => undef
|
}
|
}
|
},
|
},
|
|
'description' => 'AEMB 32-bit Microprocessor Core
|
|
For more information check http://opencores.org/project,aemb',
|
|
'ip_name' => 'aeMB',
|
|
'module_name' => 'aeMB_top',
|
|
'ports_order' => [
|
|
'dwb_adr_o',
|
|
'dwb_cyc_o',
|
|
'dwb_dat_o',
|
|
'dwb_sel_o',
|
|
'dwb_stb_o',
|
|
'dwb_tag_o',
|
|
'dwb_wre_o',
|
|
'dwb_cti_o',
|
|
'dwb_bte_o',
|
|
'dwb_ack_i',
|
|
'dwb_dat_i',
|
|
'dwb_err_i',
|
|
'dwb_rty_i',
|
|
'iwb_adr_o',
|
|
'iwb_cyc_o',
|
|
'iwb_sel_o',
|
|
'iwb_stb_o',
|
|
'iwb_tag_o',
|
|
'iwb_wre_o',
|
|
'iwb_dat_o',
|
|
'iwb_cti_o',
|
|
'iwb_bte_o',
|
|
'iwb_ack_i',
|
|
'iwb_dat_i',
|
|
'iwb_err_i',
|
|
'iwb_rty_i',
|
|
'clk',
|
|
'reset',
|
|
'sys_int_i',
|
|
'sys_ena_i'
|
|
],
|
|
'parameters_order' => [
|
|
'AEMB_IWB',
|
|
'AEMB_DWB',
|
|
'AEMB_XWB',
|
|
'AEMB_ICH',
|
|
'AEMB_IDX',
|
|
'AEMB_BSF',
|
|
'AEMB_MUL',
|
|
'STACK_SIZE',
|
|
'HEAP_SIZE'
|
|
],
|
|
'file_name' => 'mpsoc/src_processor/aeMB/verilog/aemb.v',
|
|
'gui_status' => {
|
|
'status' => 'ideal',
|
|
'timeout' => 0
|
|
},
|
|
'modules' => {
|
|
'aeMB_top' => {}
|
|
},
|
'hdl_files' => [
|
'hdl_files' => [
|
'/mpsoc/src_processor/aeMB/verilog/aemb.v',
|
'/mpsoc/src_processor/aeMB/verilog/aemb.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_core.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_xecu.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB_sim.v',
|
| Line 115... |
Line 231... |
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_edk62.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_sim.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iche.v',
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
|
'/mpsoc/src_processor/aeMB/verilog/src/aeMB2_iwbif.v'
|
],
|
],
|
'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/aeMB/verilog/aemb.v',
|
|
'module_name' => 'aeMB_top',
|
|
'sockets' => {
|
|
'interrupt_cpu' => {
|
|
'connection_num' => 'single connection',
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'interrupt_cpu'
|
|
},
|
|
'value' => 1
|
|
}
|
|
},
|
|
'version' => 2,
|
|
'description' => 'AEMB 32-bit Microprocessor Core
|
|
For more information check http://opencores.org/project,aemb',
|
|
'gen_sw_files' => [
|
'gen_sw_files' => [
|
'/mpsoc/src_processor/aeMB/sw/compile/gccromfrename_sep_tcompile/gccrom',
|
'/mpsoc/src_processor/aeMB/sw/link.ldfrename_sep_tlink.ld'
|
'/mpsoc/src_processor/aeMB/sw/Makefilefrename_sep_tMakefile'
|
|
],
|
],
|
'plugs' => {
|
'sw_files' => [
|
'enable' => {
|
'/mpsoc/src_processor/aeMB/sw/aemb',
|
'type' => 'num',
|
'/mpsoc/src_processor/aeMB/sw/aemb.specs',
|
'0' => {
|
'/mpsoc/src_processor/aeMB/sw/Makefile'
|
'name' => 'enable'
|
],
|
},
|
'unused' => undef,
|
'value' => 1,
|
'category' => 'Processor',
|
'enable' => {}
|
'version' => 10,
|
|
'ports' => {
|
|
'dwb_wre_o' => {
|
|
'type' => 'output',
|
|
'intfc_port' => 'we_o',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'range' => ''
|
},
|
},
|
'clk' => {
|
'dwb_ack_i' => {
|
'clk' => {},
|
'range' => '',
|
'value' => 1,
|
'intfc_name' => 'plug:wb_master[1]',
|
'0' => {
|
'type' => 'input',
|
'name' => 'clk'
|
'intfc_port' => 'ack_i'
|
},
|
},
|
'type' => 'num'
|
'iwb_bte_o' => {
|
|
'range' => '1:0',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'type' => 'output',
|
|
'intfc_port' => 'bte_o'
|
},
|
},
|
'wb_master' => {
|
'iwb_wre_o' => {
|
'wb_master' => {},
|
'range' => '',
|
'1' => {
|
'intfc_name' => 'plug:wb_master[0]',
|
'name' => 'dwb'
|
'type' => 'output',
|
|
'intfc_port' => 'we_o'
|
},
|
},
|
'value' => 2,
|
'iwb_ack_i' => {
|
'type' => 'num',
|
'type' => 'input',
|
'0' => {
|
'intfc_port' => 'ack_i',
|
'name' => 'iwb'
|
'range' => '',
|
}
|
'intfc_name' => 'plug:wb_master[0]'
|
},
|
},
|
'reset' => {
|
'dwb_adr_o' => {
|
'reset' => {},
|
'range' => '31:0',
|
'0' => {
|
'intfc_name' => 'plug:wb_master[1]',
|
'name' => 'reset'
|
'intfc_port' => 'adr_o',
|
|
'type' => 'output'
|
},
|
},
|
'type' => 'num',
|
'clk' => {
|
'value' => 1
|
'intfc_port' => 'clk_i',
|
}
|
'type' => 'input',
|
|
'intfc_name' => 'plug:clk[0]',
|
|
'range' => ''
|
},
|
},
|
'ports' => {
|
|
'iwb_tag_o' => {
|
'iwb_tag_o' => {
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'tag_o',
|
'intfc_port' => 'tag_o',
|
'range' => '2:0'
|
|
},
|
|
'iwb_adr_o' => {
|
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'adr_o',
|
'range' => '2:0'
|
'range' => '31:0'
|
|
},
|
},
|
'clk' => {
|
'iwb_err_i' => {
|
'range' => '',
|
'range' => '',
|
'intfc_port' => 'clk_i',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_name' => 'plug:clk[0]'
|
'intfc_port' => 'err_i'
|
},
|
},
|
'dwb_rty_i' => {
|
'dwb_cti_o' => {
|
'type' => 'input',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_port' => 'rty_i',
|
'range' => '2:0',
|
'range' => ''
|
'intfc_port' => 'cti_o',
|
|
'type' => 'output'
|
},
|
},
|
'dwb_stb_o' => {
|
'dwb_cyc_o' => {
|
'range' => '',
|
|
'intfc_port' => 'stb_o',
|
|
'type' => 'output',
|
'type' => 'output',
|
|
'intfc_port' => 'cyc_o',
|
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_name' => 'plug:wb_master[1]'
|
},
|
},
|
'dwb_wre_o' => {
|
'dwb_err_i' => {
|
'range' => '',
|
'range' => '',
|
'intfc_port' => 'we_o',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'output'
|
|
},
|
|
'iwb_stb_o' => {
|
|
'range' => '',
|
|
'intfc_port' => 'stb_o',
|
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[0]'
|
|
},
|
|
'reset' => {
|
|
'intfc_name' => 'plug:reset[0]',
|
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'reset_i',
|
'intfc_port' => 'err_i'
|
'range' => ''
|
|
},
|
},
|
'dwb_bte_o' => {
|
'dwb_bte_o' => {
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_port' => 'bte_o',
|
'range' => '1:0',
|
'range' => '1:0'
|
'type' => 'output',
|
|
'intfc_port' => 'bte_o'
|
},
|
},
|
'dwb_dat_i' => {
|
'iwb_cti_o' => {
|
'range' => '31:0',
|
'intfc_port' => 'cti_o',
|
'intfc_port' => 'dat_i',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => '2:0',
|
'type' => 'input'
|
'intfc_name' => 'plug:wb_master[0]'
|
},
|
},
|
'dwb_dat_o' => {
|
'iwb_adr_o' => {
|
'range' => '31:0',
|
|
'intfc_port' => 'dat_o',
|
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_port' => 'adr_o',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'range' => '31:0'
|
},
|
},
|
'iwb_rty_i' => {
|
'sys_ena_i' => {
|
|
'intfc_name' => 'plug:enable[0]',
|
'range' => '',
|
'range' => '',
|
'intfc_port' => 'rty_i',
|
'intfc_port' => 'enable_i',
|
'type' => 'input',
|
'type' => 'input'
|
'intfc_name' => 'plug:wb_master[0]'
|
|
},
|
},
|
'iwb_cyc_o' => {
|
'iwb_cyc_o' => {
|
'intfc_port' => 'cyc_o',
|
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'cyc_o',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'dwb_cyc_o' => {
|
'dwb_dat_o' => {
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'range' => '31:0',
|
'type' => 'output',
|
'type' => 'output',
|
'range' => '',
|
'intfc_port' => 'dat_o'
|
'intfc_port' => 'cyc_o'
|
|
},
|
|
'dwb_sel_o' => {
|
|
'intfc_port' => 'sel_o',
|
|
'range' => '3:0',
|
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[1]'
|
|
},
|
},
|
'sys_int_i' => {
|
'dwb_stb_o' => {
|
'intfc_port' => 'int_i',
|
|
'range' => '',
|
'range' => '',
|
'type' => 'input',
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'socket:interrupt_cpu[0]'
|
'intfc_port' => 'stb_o',
|
|
'type' => 'output'
|
},
|
},
|
'iwb_dat_i' => {
|
'iwb_rty_i' => {
|
'intfc_port' => 'dat_i',
|
'range' => '',
|
'range' => '31:0',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'intfc_port' => 'rty_i',
|
'type' => 'input'
|
'type' => 'input'
|
},
|
},
|
'dwb_err_i' => {
|
'iwb_stb_o' => {
|
'intfc_port' => 'err_i',
|
'intfc_name' => 'plug:wb_master[0]',
|
'range' => '',
|
'range' => '',
|
|
'type' => 'output',
|
|
'intfc_port' => 'stb_o'
|
|
},
|
|
'dwb_dat_i' => {
|
|
'range' => '31:0',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_name' => 'plug:wb_master[1]'
|
'intfc_port' => 'dat_i'
|
},
|
},
|
'iwb_sel_o' => {
|
'iwb_sel_o' => {
|
|
'intfc_port' => 'sel_o',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_port' => 'sel_o',
|
|
'range' => '3:0'
|
'range' => '3:0'
|
},
|
},
|
'iwb_wre_o' => {
|
'dwb_sel_o' => {
|
'intfc_port' => 'we_o',
|
'intfc_port' => 'sel_o',
|
'range' => '',
|
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[0]'
|
|
},
|
|
'dwb_adr_o' => {
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'output',
|
'range' => '3:0'
|
'intfc_port' => 'adr_o',
|
|
'range' => '31:0'
|
|
},
|
},
|
'iwb_cti_o' => {
|
'iwb_dat_o' => {
|
'range' => '2:0',
|
'range' => '31:0',
|
'intfc_port' => 'cti_o',
|
'intfc_name' => 'plug:wb_master[0]',
|
'type' => 'output',
|
'type' => 'output',
|
'intfc_name' => 'plug:wb_master[0]'
|
'intfc_port' => 'dat_o'
|
},
|
},
|
'iwb_err_i' => {
|
'sys_int_i' => {
|
'intfc_port' => 'err_i',
|
'type' => 'input',
|
|
'intfc_port' => 'int_i',
|
'range' => '',
|
'range' => '',
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'socket:interrupt_cpu[0]'
|
'type' => 'input'
|
|
},
|
|
'dwb_tag_o' => {
|
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
|
'intfc_port' => 'tag_o',
|
|
'range' => '2:0'
|
|
},
|
},
|
'sys_ena_i' => {
|
'iwb_dat_i' => {
|
'intfc_name' => 'plug:enable[0]',
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'range' => '31:0',
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'enable_i',
|
'intfc_port' => 'dat_i'
|
'range' => ''
|
|
},
|
},
|
'dwb_ack_i' => {
|
'dwb_rty_i' => {
|
'range' => '',
|
'range' => '',
|
'intfc_port' => 'ack_i',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'type' => 'input'
|
'type' => 'input',
|
},
|
'intfc_port' => 'rty_i'
|
'iwb_bte_o' => {
|
|
'range' => '1:0',
|
|
'intfc_port' => 'bte_o',
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'type' => 'output'
|
|
},
|
},
|
'iwb_dat_o' => {
|
'reset' => {
|
'intfc_name' => 'plug:wb_master[0]',
|
'intfc_name' => 'plug:reset[0]',
|
'type' => 'output',
|
'range' => '',
|
'intfc_port' => 'dat_o',
|
'type' => 'input',
|
'range' => '31:0'
|
'intfc_port' => 'reset_i'
|
},
|
},
|
'dwb_cti_o' => {
|
'dwb_tag_o' => {
|
'type' => 'output',
|
|
'intfc_name' => 'plug:wb_master[1]',
|
'intfc_name' => 'plug:wb_master[1]',
|
'range' => '2:0',
|
'range' => '2:0',
|
'intfc_port' => 'cti_o'
|
'type' => 'output',
|
},
|
'intfc_port' => 'tag_o'
|
'iwb_ack_i' => {
|
|
'intfc_name' => 'plug:wb_master[0]',
|
|
'type' => 'input',
|
|
'intfc_port' => 'ack_i',
|
|
'range' => ''
|
|
}
|
}
|
},
|
},
|
'gui_status' => {
|
'system_c' => '
|
'status' => 'ideal',
|
#include "aemb/core.cc"
|
'timeout' => 0
|
|
},
|
|
'modules' => {
|
|
'aeMB_top' => {}
|
|
},
|
|
'ip_name' => 'aeMB',
|
|
'system_h' => ' #include
|
|
#include
|
|
#include "aemb/core.hh"
|
|
|
|
inline void nop (void) {
|
/*!
|
asm volatile ("nop");
|
* Assembly macro to enable MSR_IE
|
}',
|
*/
|
'ports_order' => [
|
void aemb_enable_interrupt ()
|
'dwb_adr_o',
|
{
|
'dwb_cyc_o',
|
int msr, tmp;
|
'dwb_dat_o',
|
asm volatile ("mfs %0, rmsr;"
|
'dwb_sel_o',
|
"ori %1, %0, 0x02;"
|
'dwb_stb_o',
|
"mts rmsr, %1;"
|
'dwb_tag_o',
|
: "=r"(msr)
|
'dwb_wre_o',
|
: "r" (tmp)
|
'dwb_cti_o',
|
);
|
'dwb_bte_o',
|
}
|
'dwb_ack_i',
|
|
'dwb_dat_i',
|
void aemb_disable_interrupt ()
|
'dwb_err_i',
|
{
|
'dwb_rty_i',
|
int msr, tmp;
|
'iwb_adr_o',
|
asm volatile ("mfs %0, rmsr;"
|
'iwb_cyc_o',
|
"andi %1, %0, 0xFD;"
|
'iwb_sel_o',
|
"mts rmsr, %1;"
|
'iwb_stb_o',
|
: "=r"(msr)
|
'iwb_tag_o',
|
: "r" (tmp)
|
'iwb_wre_o',
|
);
|
'iwb_dat_o',
|
}
|
'iwb_cti_o',
|
|
'iwb_bte_o',
|
|
'iwb_ack_i',
|
/* Loops/exits simulation */
|
'iwb_dat_i',
|
void exit (int i)
|
'iwb_err_i',
|
{
|
'iwb_rty_i',
|
aemb_disable_interrupt ();
|
'clk',
|
while (1);
|
'reset',
|
}
|
'sys_int_i',
|
|
'sys_ena_i'
|
|
],
|
|
'category' => 'Processor',
|
|
'sw_files' => [
|
'
|
'/mpsoc/src_processor/aeMB/sw/aemb',
|
|
'/mpsoc/src_processor/aeMB/sw/compile',
|
|
'/mpsoc/src_processor/aeMB/sw/program',
|
|
'/mpsoc/src_processor/program.sh',
|
|
'/mpsoc/src_processor/aeMB/sw/define_printf.h'
|
|
],
|
|
'parameters_order' => [
|
|
'AEMB_IWB',
|
|
'AEMB_DWB',
|
|
'AEMB_XWB',
|
|
'AEMB_ICH',
|
|
'AEMB_IDX',
|
|
'AEMB_BSF',
|
|
'AEMB_MUL',
|
|
'STACK_SIZE',
|
|
'HEAP_SIZE'
|
|
]
|
|
}, 'ip_gen' );
|
}, 'ip_gen' );
|
