| Line 1... |
Line 1... |
#######################################################################
|
#######################################################################
|
## File: single_port_ram.IP
|
## File: single_port_ram.IP
|
##
|
##
|
## Copyright (C) 2014-2016 Alireza Monemi
|
## Copyright (C) 2014-2016 Alireza Monemi
|
##
|
##
|
## This file is part of ProNoC 1.6.0
|
## This file is part of ProNoC 1.8.0
|
##
|
##
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
## MAY CAUSE UNEXPECTED BEHAIVOR.
|
################################################################################
|
################################################################################
|
|
|
$wb_single_port_ram = bless( {
|
$ipgen = bless( {
|
'modules' => {
|
'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf',
|
'wb_single_port_ram' => {}
|
|
},
|
|
'module_name' => 'wb_single_port_ram',
|
|
'version' => 19,
|
|
'category' => 'RAM',
|
|
'description' => 'Single port ram with wishbone bus interface.',
|
|
'plugs' => {
|
|
'reset' => {
|
|
'value' => 1,
|
|
'reset' => {},
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'reset'
|
|
}
|
|
},
|
|
'wb_slave' => {
|
|
'value' => 1,
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'wb',
|
|
'width' => 'WB_Aw',
|
|
'addr' => '0x0000_0000 0x3fff_ffff RAM'
|
|
},
|
|
'wb_slave' => {}
|
|
},
|
|
'clk' => {
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'clk'
|
|
},
|
|
'value' => 1,
|
|
'clk' => {}
|
|
}
|
|
},
|
|
'unused' => undef,
|
'unused' => undef,
|
'ip_name' => 'single_port_ram',
|
|
'hdl_files' => [
|
|
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
|
'/mpsoc/src_peripheral/ram/generic_ram.v',
|
|
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
|
|
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
|
|
],
|
|
'parameters_order' => [
|
|
'Dw',
|
|
'Aw',
|
|
'BYTE_WR_EN',
|
|
'FPGA_VENDOR',
|
|
'JTAG_CONNECT',
|
|
'JTAG_INDEX',
|
|
'TAGw',
|
|
'SELw',
|
|
'CTIw',
|
|
'BTEw',
|
|
'WB_Aw',
|
|
'BURST_MODE',
|
|
'MEM_CONTENT_FILE_NAME',
|
|
'INITIAL_EN',
|
|
'INIT_FILE_PATH'
|
|
],
|
|
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
|
'gui_status' => {
|
'gui_status' => {
|
'timeout' => 0,
|
'timeout' => 0,
|
'status' => 'ideal'
|
'status' => 'ideal'
|
},
|
},
|
|
'modules' => {
|
|
'wb_single_port_ram' => {}
|
|
},
|
'parameters' => {
|
'parameters' => {
|
'SELw' => {
|
'Aw' => {
|
|
'global_param' => 'Parameter',
|
|
'info' => 'Memory address width',
|
|
'type' => 'Spin-button',
|
|
'redefine_param' => 1,
|
|
'default' => '12',
|
|
'content' => '4,31,1'
|
|
},
|
|
'INITIAL_EN' => {
|
|
'content' => '"YES","NO"',
|
|
'redefine_param' => 1,
|
|
'default' => '"NO"',
|
|
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
|
|
'type' => 'Combo-box',
|
|
'global_param' => 'Localparam'
|
|
},
|
|
'WB_Aw' => {
|
|
'global_param' => 'Don\'t include',
|
|
'info' => undef,
|
|
'type' => 'Fixed',
|
|
'redefine_param' => 1,
|
|
'default' => 'Aw+2',
|
|
'content' => ''
|
|
},
|
|
'BYTE_WR_EN' => {
|
|
'info' => 'Byte enable',
|
|
'type' => 'Combo-box',
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
|
'content' => '"YES","NO"',
|
|
'default' => '"YES"'
|
|
},
|
|
'TAGw' => {
|
|
'global_param' => 'Localparam',
|
|
'info' => 'Parameter',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'content' => '',
|
'content' => '',
|
'deafult' => 'Dw/8',
|
'default' => '3',
|
'info' => 'Parameter'
|
'redefine_param' => 1
|
|
},
|
|
'FPGA_VENDOR' => {
|
|
'content' => '"ALTERA","GENERIC"',
|
|
'redefine_param' => 1,
|
|
'default' => '"GENERIC"',
|
|
'info' => '',
|
|
'type' => 'Combo-box',
|
|
'global_param' => 'Localparam'
|
},
|
},
|
|
|
'MEM_CONTENT_FILE_NAME' => {
|
'MEM_CONTENT_FILE_NAME' => {
|
'type' => 'Entry',
|
'default' => '"ram0"',
|
'content' => '',
|
'content' => '',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Localparam',
|
'type' => 'Entry',
|
'info' => 'MEM_FILE_NAME:
|
'info' => 'MEM_FILE_NAME:
|
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
|
The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.
|
|
|
File Path:
|
File Path:
|
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
|
For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.
|
| Line 99... |
Line 82... |
|
|
file_type:
|
file_type:
|
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
|
bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.
|
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
|
memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.
|
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
|
mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ',
|
'deafult' => '"ram0"'
|
'global_param' => 'Localparam'
|
},
|
|
'JTAG_CONNECT' => {
|
|
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"',
|
|
'type' => 'Combo-box',
|
|
'global_param' => 'Localparam',
|
|
'redefine_param' => 1,
|
|
'deafult' => '"DISABLED"',
|
|
'info' => 'JTAG_CONNECT:
|
|
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. '
|
|
},
|
},
|
'WB_Aw' => {
|
'Dw' => {
|
'deafult' => 'Aw+2',
|
'content' => '8,1024,1',
|
'info' => undef,
|
|
'global_param' => 'Don\'t include',
|
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'type' => 'Fixed',
|
'default' => '32',
|
'content' => ''
|
'global_param' => 'Parameter',
|
|
'info' => 'Memory data width in Bits.',
|
|
'type' => 'Spin-button'
|
},
|
},
|
|
|
'JTAG_INDEX' => {
|
'JTAG_INDEX' => {
|
'global_param' => 'Localparam',
|
|
'redefine_param' => 1,
|
|
'content' => '',
|
'content' => '',
|
'type' => 'Entry',
|
'default' => 'CORE_ID',
|
'deafult' => 'CORE_ID',
|
'redefine_param' => 1,
|
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
|
'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.
|
|
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
|
In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).
|
|
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
|
You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).
|
|
|
'
|
',
|
},
|
'type' => 'Entry',
|
'Aw' => {
|
'global_param' => 'Localparam'
|
'info' => 'Memory address width',
|
|
'deafult' => '12',
|
|
'content' => '4,31,1',
|
|
'type' => 'Spin-button',
|
|
'redefine_param' => 1,
|
|
'global_param' => 'Parameter'
|
|
},
|
},
|
'TAGw' => {
|
'CTIw' => {
|
|
'content' => '',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
|
'default' => '3',
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
'content' => '',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'info' => 'Parameter',
|
'info' => 'Parameter'
|
'deafult' => '3'
|
|
},
|
},
|
'BTEw' => {
|
'SELw' => {
|
'deafult' => '2',
|
'content' => '',
|
|
'redefine_param' => 1,
|
|
'default' => 'Dw/8',
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'content' => '',
|
'global_param' => 'Localparam'
|
'global_param' => 'Localparam',
|
|
'redefine_param' => 1
|
|
},
|
},
|
'FPGA_VENDOR' => {
|
'BURST_MODE' => {
|
'type' => 'Combo-box',
|
'default' => '"ENABLED"',
|
'content' => '"ALTERA","GENERIC"',
|
'content' => '"DISABLED","ENABLED"',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Localparam',
|
'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ',
|
'info' => '',
|
'type' => 'Combo-box',
|
'deafult' => '"GENERIC"'
|
'global_param' => 'Localparam'
|
},
|
},
|
'CTIw' => {
|
'BTEw' => {
|
'type' => 'Fixed',
|
|
'content' => '',
|
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Localparam',
|
'default' => '2',
|
|
'content' => '',
|
|
'type' => 'Fixed',
|
'info' => 'Parameter',
|
'info' => 'Parameter',
|
'deafult' => '3'
|
'global_param' => 'Localparam'
|
},
|
|
'Dw' => {
|
|
'type' => 'Spin-button',
|
|
'content' => '8,1024,1',
|
|
'redefine_param' => 1,
|
|
'global_param' => 'Parameter',
|
|
'info' => 'Memory data width in Bits.',
|
|
'deafult' => '32'
|
|
},
|
},
|
'INIT_FILE_PATH' => {
|
'INIT_FILE_PATH' => {
|
'info' => undef,
|
|
'deafult' => 'SW_LOC',
|
|
'redefine_param' => 1,
|
|
'global_param' => 'Localparam',
|
|
'type' => 'Fixed',
|
'type' => 'Fixed',
|
'content' => ''
|
'info' => undef,
|
},
|
|
|
|
'INITIAL_EN' => {
|
|
'deafult' => '"NO"',
|
|
'info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.',
|
|
'global_param' => 'Localparam',
|
|
'redefine_param' => 1,
|
|
'content' => '"YES","NO"',
|
|
'type' => 'Combo-box'
|
|
},
|
|
'BURST_MODE' => {
|
|
'deafult' => '"ENABLED"',
|
|
'info' => 'Wishbone bus burst read/write mode enable/disable. ',
|
|
'type' => 'Combo-box',
|
|
'content' => '"DISABLED","ENABLED"',
|
|
'global_param' => 'Localparam',
|
'global_param' => 'Localparam',
|
|
'content' => '',
|
|
'default' => 'SW_LOC',
|
'redefine_param' => 1
|
'redefine_param' => 1
|
},
|
},
|
'BYTE_WR_EN' => {
|
'JTAG_CONNECT' => {
|
'info' => '',
|
|
'deafult' => '"YES"',
|
|
'type' => 'Combo-box',
|
'type' => 'Combo-box',
|
'content' => '"YES","NO"',
|
'info' => 'JTAG_CONNECT:
|
|
if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ',
|
|
'global_param' => 'Localparam',
|
|
'default' => '"DISABLED"',
|
'redefine_param' => 1,
|
'redefine_param' => 1,
|
'global_param' => 'Localparam'
|
'content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'
|
}
|
}
|
},
|
},
|
'ports_order' => [
|
'version' => 22,
|
'clk',
|
|
'reset',
|
|
'sa_dat_i',
|
|
'sa_sel_i',
|
|
'sa_addr_i',
|
|
'sa_tag_i',
|
|
'sa_cti_i',
|
|
'sa_bte_i',
|
|
'sa_stb_i',
|
|
'sa_cyc_i',
|
|
'sa_we_i',
|
|
'sa_dat_o',
|
|
'sa_ack_o',
|
|
'sa_err_o',
|
|
'sa_rty_o'
|
|
],
|
|
'ports' => {
|
'ports' => {
|
'sa_cyc_i' => {
|
'reset' => {
|
'intfc_port' => 'cyc_i',
|
'type' => 'input',
|
|
'range' => '',
|
|
'intfc_port' => 'reset_i',
|
|
'intfc_name' => 'plug:reset[0]'
|
|
},
|
|
'sa_bte_i' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'bte_i',
|
'type' => 'input',
|
'type' => 'input',
|
'range' => ''
|
'range' => 'BTEw-1 : 0'
|
},
|
},
|
'sa_ack_o' => {
|
'sa_ack_o' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'ack_o',
|
'intfc_port' => 'ack_o',
|
'range' => '',
|
'range' => '',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'sa_dat_o' => {
|
'sa_sel_i' => {
|
'intfc_port' => 'dat_o',
|
'intfc_port' => 'sel_i',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'range' => 'Dw-1 : 0',
|
'range' => 'SELw-1 : 0',
|
'type' => 'output'
|
'type' => 'input'
|
},
|
},
|
'sa_addr_i' => {
|
'sa_err_o' => {
|
'intfc_port' => 'adr_i',
|
'type' => 'output',
|
|
'range' => '',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'type' => 'input',
|
'intfc_port' => 'err_o'
|
'range' => 'Aw-1 : 0'
|
|
},
|
},
|
'sa_tag_i' => {
|
'sa_tag_i' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'tag_i',
|
'intfc_port' => 'tag_i',
|
'type' => 'input',
|
'type' => 'input',
|
'range' => 'TAGw-1 : 0'
|
'range' => 'TAGw-1 : 0'
|
},
|
},
|
'sa_dat_i' => {
|
'sa_dat_i' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'type' => 'input',
|
'intfc_port' => 'dat_i',
|
|
'range' => 'Dw-1 : 0',
|
'range' => 'Dw-1 : 0',
|
'type' => 'input'
|
'intfc_port' => 'dat_i',
|
|
'intfc_name' => 'plug:wb_slave[0]'
|
},
|
},
|
'sa_stb_i' => {
|
'sa_cyc_i' => {
|
'type' => 'input',
|
|
'range' => '',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'stb_i'
|
'intfc_port' => 'cyc_i',
|
|
'type' => 'input',
|
|
'range' => ''
|
},
|
},
|
'sa_rty_o' => {
|
'sa_rty_o' => {
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'rty_o',
|
'intfc_port' => 'rty_o',
|
'range' => '',
|
'range' => '',
|
'type' => 'output'
|
'type' => 'output'
|
},
|
},
|
'sa_we_i' => {
|
'sa_cti_i' => {
|
'intfc_port' => 'we_i',
|
'range' => 'CTIw-1 : 0',
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'range' => '',
|
|
'type' => 'input'
|
|
},
|
|
'sa_sel_i' => {
|
|
'type' => 'input',
|
'type' => 'input',
|
'range' => 'SELw-1 : 0',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_port' => 'sel_i'
|
'intfc_port' => 'cti_i'
|
},
|
},
|
'sa_cti_i' => {
|
'sa_we_i' => {
|
'range' => 'CTIw-1 : 0',
|
|
'type' => 'input',
|
'type' => 'input',
|
'intfc_port' => 'cti_i',
|
'range' => '',
|
|
'intfc_port' => 'we_i',
|
'intfc_name' => 'plug:wb_slave[0]'
|
'intfc_name' => 'plug:wb_slave[0]'
|
},
|
},
|
|
'sa_dat_o' => {
|
|
'intfc_port' => 'dat_o',
|
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'type' => 'output',
|
|
'range' => 'Dw-1 : 0'
|
|
},
|
'clk' => {
|
'clk' => {
|
'intfc_name' => 'plug:clk[0]',
|
|
'intfc_port' => 'clk_i',
|
|
'type' => 'input',
|
'type' => 'input',
|
'range' => ''
|
'range' => '',
|
|
'intfc_name' => 'plug:clk[0]',
|
|
'intfc_port' => 'clk_i'
|
},
|
},
|
'sa_bte_i' => {
|
'sa_stb_i' => {
|
'intfc_port' => 'bte_i',
|
'intfc_name' => 'plug:wb_slave[0]',
|
|
'intfc_port' => 'stb_i',
|
|
'range' => '',
|
|
'type' => 'input'
|
|
},
|
|
'sa_addr_i' => {
|
|
'intfc_port' => 'adr_i',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'intfc_name' => 'plug:wb_slave[0]',
|
'range' => 'BTEw-1 : 0',
|
'range' => 'Aw-1 : 0',
|
'type' => 'input'
|
'type' => 'input'
|
|
}
|
},
|
},
|
|
'parameters_order' => [
|
|
'Dw',
|
|
'Aw',
|
|
'BYTE_WR_EN',
|
|
'FPGA_VENDOR',
|
|
'JTAG_CONNECT',
|
|
'JTAG_INDEX',
|
|
'TAGw',
|
|
'SELw',
|
|
'CTIw',
|
|
'BTEw',
|
|
'WB_Aw',
|
|
'BURST_MODE',
|
|
'MEM_CONTENT_FILE_NAME',
|
|
'INITIAL_EN',
|
|
'INIT_FILE_PATH'
|
|
],
|
|
'plugs' => {
|
'reset' => {
|
'reset' => {
|
'range' => '',
|
'0' => {
|
'type' => 'input',
|
'name' => 'reset'
|
'intfc_port' => 'reset_i',
|
|
'intfc_name' => 'plug:reset[0]'
|
|
},
|
},
|
'sa_err_o' => {
|
'type' => 'num',
|
'intfc_port' => 'err_o',
|
'value' => 1,
|
'intfc_name' => 'plug:wb_slave[0]',
|
'reset' => {}
|
'range' => '',
|
},
|
'type' => 'output'
|
'wb_slave' => {
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'wb',
|
|
'addr' => '0x0000_0000 0x3fff_ffff RAM',
|
|
'width' => 'WB_Aw'
|
|
},
|
|
'wb_slave' => {},
|
|
'value' => 1
|
|
},
|
|
'clk' => {
|
|
'value' => 1,
|
|
'clk' => {},
|
|
'type' => 'num',
|
|
'0' => {
|
|
'name' => 'clk'
|
}
|
}
|
}
|
}
|
|
},
|
|
'hdl_files' => [
|
|
'/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
|
'/mpsoc/src_peripheral/ram/generic_ram.v',
|
|
'/mpsoc/src_peripheral/ram/byte_enabled_generic_ram.sv',
|
|
'/mpsoc/src_peripheral/ram/wb_bram_ctrl.v'
|
|
],
|
|
'ip_name' => 'single_port_ram',
|
|
'ports_order' => [
|
|
'clk',
|
|
'reset',
|
|
'sa_dat_i',
|
|
'sa_sel_i',
|
|
'sa_addr_i',
|
|
'sa_tag_i',
|
|
'sa_cti_i',
|
|
'sa_bte_i',
|
|
'sa_stb_i',
|
|
'sa_cyc_i',
|
|
'sa_we_i',
|
|
'sa_dat_o',
|
|
'sa_ack_o',
|
|
'sa_err_o',
|
|
'sa_rty_o'
|
|
],
|
|
'module_name' => 'wb_single_port_ram',
|
|
'description' => 'Single port ram with wishbone bus interface.',
|
|
'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/ram/wb_single_port_ram.v',
|
|
'category' => 'RAM'
|
}, 'ip_gen' );
|
}, 'ip_gen' );
|
