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#######################################################################
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#######################################################################
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## File: clk_source.IP
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## File: clk_source.IP
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##
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##
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## Copyright (C) 2014-2016 Alireza Monemi
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## Copyright (C) 2014-2019 Alireza Monemi
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##
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##
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## This file is part of ProNoC 1.5.0
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## This file is part of ProNoC 1.9.1
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##
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##
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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## MAY CAUSE UNEXPECTED BEHAIVOR.
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################################################################################
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################################################################################
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$clk_source = bless( {
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$ipgen = bless( {
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'hdl_files' => [
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'version' => 1,
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'/mpsoc/src_peripheral/reset_sync/altera_reset_synchronizer.v',
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'unused' => undef,
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'/mpsoc/src_peripheral/reset_sync/clk_source.v'
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'parameters' => {
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],
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'FPGA_VENDOR' => {
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'ip_name' => 'clk_source',
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'content' => '"ALTERA","XILINX"',
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'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.',
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'info' => '',
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'gui_status' => {
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'default' => '"ALTERA"',
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'status' => 'ideal',
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'type' => 'Combo-box',
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'timeout' => 0
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'global_param' => 'Localparam',
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},
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'redefine_param' => 1
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'modules' => {
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'clk_source' => {}
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},
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'plugs' => {
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'reset' => {
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'reset' => {},
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'0' => {
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'name' => 'reset'
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},
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'value' => 1,
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'type' => 'num'
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},
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'clk' => {
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'clk' => {},
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'0' => {
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'name' => 'clk'
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},
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'value' => 1,
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'type' => 'num'
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}
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}
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},
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},
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'category' => 'Source',
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'ip_name' => 'clk_source',
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'hdl_files' => [
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'/mpsoc/rtl/src_peripheral/clk_source/altera_reset_synchronizer.v',
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'/mpsoc/rtl/src_peripheral/clk_source/clk_source.v',
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'/mpsoc/rtl/src_peripheral/clk_source/xilinx_reset_synchroniser.v'
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],
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'file_name' => 'mpsoc/rtl/src_peripheral/clk_source/clk_source.v',
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'parameters_order' => [
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'FPGA_VENDOR'
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],
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'ports' => {
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'ports' => {
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'clk_out' => {
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'reset_in' => {
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'intfc_port' => 'clk_o',
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'intfc_port' => 'reset_i',
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'intfc_name' => 'socket:clk[0]',
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'range' => '',
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'type' => 'output'
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},
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'reset_out' => {
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'intfc_port' => 'reset_o',
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'intfc_name' => 'socket:reset[0]',
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'range' => '',
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'range' => '',
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'type' => 'output'
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'type' => 'input',
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'intfc_name' => 'plug:reset[0]'
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},
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},
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'clk_in' => {
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'clk_in' => {
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'intfc_port' => 'clk_i',
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'intfc_name' => 'plug:clk[0]',
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'intfc_name' => 'plug:clk[0]',
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'type' => 'input',
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'range' => '',
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'range' => '',
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'type' => 'input'
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'intfc_port' => 'clk_i'
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},
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},
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'reset_in' => {
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'reset_out' => {
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'intfc_port' => 'reset_i',
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'range' => '',
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'intfc_name' => 'plug:reset[0]',
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'intfc_port' => 'reset_o',
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'type' => 'output',
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'intfc_name' => 'socket:reset[0]'
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},
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'clk_out' => {
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'intfc_port' => 'clk_o',
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'range' => '',
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'range' => '',
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'type' => 'input'
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'type' => 'output',
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'intfc_name' => 'socket:clk[0]'
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}
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}
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},
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},
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'file_name' => '/home/alireza/Mywork/mpsoc/src_peripheral/reset_sync/clk_source.v',
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'description' => 'clk source. This module provides the clk and reset (socket) interfaces for all other IPs. It also synchronizes the reset signal.',
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'gui_status' => {
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'timeout' => 0,
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'status' => 'ideal'
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},
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'sockets' => {
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'sockets' => {
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'clk' => {
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'clk' => {
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'clk' => {},
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'connection_num' => 'multi connection',
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'value' => 1,
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'value' => 1,
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'0' => {
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'0' => {
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'name' => 'clk'
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'name' => 'clk'
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},
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},
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'connection_num' => 'multi connection',
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'clk' => {},
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'type' => 'num'
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'type' => 'num'
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},
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},
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'reset' => {
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'reset' => {
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'reset' => {},
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'connection_num' => 'multi connection',
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'connection_num' => 'multi connection',
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'value' => 1,
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'value' => 1,
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'0' => {
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'0' => {
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'name' => 'reset'
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'name' => 'reset'
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},
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},
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'reset' => {},
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'type' => 'num'
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'type' => 'num'
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}
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}
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},
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},
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'module_name' => 'clk_source',
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'modules' => {
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'unused' => undef,
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'clk_source' => {}
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'category' => 'Source'
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},
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'plugs' => {
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'reset' => {
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'reset' => {},
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'type' => 'num',
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'value' => 1,
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'0' => {
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'name' => 'reset'
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}
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},
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'clk' => {
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'type' => 'num',
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'value' => 1,
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'0' => {
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'name' => 'clk'
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},
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'clk' => {}
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}
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},
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'module_name' => 'clk_source'
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}, 'ip_gen' );
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}, 'ip_gen' );
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