URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [hdr_file_gen.pl] - Diff between revs 28 and 38

Rev 28	Rev 38
Line 62...	Line 62...
`}`	`}`



`sub generate_header_file{`	`sub generate_header_file{`
`my ($soc,$project_dir,$sw_path,$dir)= @_;`	`my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;`
`my $soc_name=$soc->object_get_attribute('soc_name');`	`my $soc_name=$soc->object_get_attribute('soc_name');`
`$soc_name = uc($soc_name);`	`$soc_name = uc($soc_name);`
`if(!defined $soc_name){$soc_name='soc'};`	`if(!defined $soc_name){$soc_name='soc'};`

`my @instances=$soc->soc_get_all_instances();`	`my @instances=$soc->soc_get_all_instances();`
Line 138...	Line 138...

`}`	`}`
`}`	`}`
`}`	`}`

	`# Write Hardware gen files`
	`my @hw_file_gen = $ip->ip_get_list($category,$module,"gen_hw_files");`
	`foreach my $file (@hw_file_gen){`
	`if(defined $file ){`
	`my ($path,$rename)=split('frename_sep_t',$file);`
	`$rename=replace_golb_var($rename,\%params);`
	`#read the file content`
	`my $content=read_file_cntent($path,$project_dir);`
	`$content=replace_golb_var($content,\%params);`


	`if(defined $rename){`

	`open(FILE, ">lib/verilog/tmp") \|\| die "Can not open: $!";`
	`print FILE $content;`
	`close(FILE) \|\| die "Error closing file: $!";`
	`move ("$dir/lib/verilog/tmp","$hw_path/$rename");`


	`}`
	`}`
	`}`



`}`	`}`

`add_text_to_string(\$system_h,"#endif\n");`	`add_text_to_string(\$system_h,"#endif\n");`
`my $name=$soc->object_get_attribute('soc_name');`	`my $name=$soc->object_get_attribute('soc_name');`