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use lib 'lib/perl';
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use lib 'lib/perl';
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use strict;
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use strict;
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use warnings;
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use warnings;
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use FindBin;
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use lib $FindBin::Bin;
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use soc;
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use soc;
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use ip;
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use ip;
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my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;
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my ($soc,$project_dir,$sw_path,$hw_path,$dir)= @_;
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my $soc_name=$soc->object_get_attribute('soc_name');
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my $soc_name=$soc->object_get_attribute('soc_name');
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$soc_name = uc($soc_name);
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$soc_name = uc($soc_name);
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if(!defined $soc_name){$soc_name='soc'};
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if(!defined $soc_name){$soc_name='soc'};
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my $name=$soc->object_get_attribute('soc_name');
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my @instances=$soc->soc_get_all_instances();
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my @instances=$soc->soc_get_all_instances();
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my $system_h="#ifndef $soc_name\_SYSTEM_H\n\t#define $soc_name\_SYSTEM_H\n";
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my $system_h="#ifndef $soc_name\_SYSTEM_H\n\t#define $soc_name\_SYSTEM_H\n";
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my $system_c="#include \"$name.h\"\n\n";
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#add_text_to_string(\$system_h, "\n #include <stdio.h> \n #include <stdlib.h> \n #include \"aemb/core.hh\"");
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#add_text_to_string(\$system_h, "\n #include <stdio.h> \n #include <stdlib.h> \n #include \"aemb/core.hh\"");
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my $ip = ip->lib_new ();
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my $ip = ip->lib_new ();
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my $module_name =$soc->soc_get_module_name($id);
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my $module_name =$soc->soc_get_module_name($id);
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my $category =$soc->soc_get_category($id);
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my $category =$soc->soc_get_category($id);
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my $inst =$soc->soc_get_instance_name($id);
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my $inst =$soc->soc_get_instance_name($id);
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add_text_to_string(\$system_h,"\n \n /* $inst */ \n");
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add_text_to_string(\$system_h,"\n \n /* $inst */ \n");
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$system_c = $system_c . "\n \n /* $inst */ \n";
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#$inst=uc($inst);
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#$inst=uc($inst);
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# print base address
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# print base address
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my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
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my @plugs= $soc->soc_get_all_plugs_of_an_instance($id);
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#intrrupt
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#intrrupt
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if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){
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if((defined $connect_socket) && ($connect_socket eq 'interrupt_peripheral')){
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add_text_to_string(\$system_h,"//intrrupt flag location\n");
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add_text_to_string(\$system_h,"//intrrupt flag location\n");
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add_text_to_string(\$system_h," #define $inst\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)==1);
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add_text_to_string(\$system_h," #define $inst\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)==1);
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add_text_to_string(\$system_h," #define $inst\_$num\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)>1);
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add_text_to_string(\$system_h," #define $inst\_$num\_INT (1<<$connect_socket_num)\n") if(scalar (@nums)>1);
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add_text_to_string(\$system_h," #define $inst\_INT_PIN $connect_socket_num\n") if(scalar (@nums)==1);
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add_text_to_string(\$system_h," #define $inst\_$num\_INT_PIN $connect_socket_num\n") if(scalar (@nums)>1);
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}
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}
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}
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}
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}
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}
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my $hdr =$ip->ip_get($category,$module,"system_h");
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my $hdr_h=$ip->ip_get($category,$module,"system_h");
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#print "$hdr";
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if(defined $hdr_h){
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$hdr_h=replace_golb_var($hdr_h,\%params);
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add_text_to_string(\$system_h,"$hdr_h\n");
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}
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# \$\{?IP(\b|\})
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my $hdr_c=$ip->ip_get($category,$module,"system_c");
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if(defined $hdr){
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if(defined $hdr_c){
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$hdr=replace_golb_var($hdr,\%params);
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$hdr_c=replace_golb_var($hdr_c,\%params);
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add_text_to_string(\$system_h,"$hdr\n");
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$system_c=$system_c."$hdr_c\n";
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}
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}
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# Write Software gen files
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# Write Software gen files
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my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files");
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my @sw_file_gen = $ip->ip_get_list($category,$module,"gen_sw_files");
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foreach my $file (@sw_file_gen){
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foreach my $file (@sw_file_gen){
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if(defined $file ){
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if(defined $file ){
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my ($path,$rename)=split('frename_sep_t',$file);
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my ($path,$rename)=split('frename_sep_t',$file);
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$rename=replace_golb_var($rename,\%params);
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$rename=replace_golb_var($rename,\%params);
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#read the file content
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#read the file content
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my $content=read_file_cntent($path,$project_dir);
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my $content=read_file_cntent($path,$project_dir);
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$content=replace_golb_var($content,\%params);
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$content=replace_golb_var($content,\%params);
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if(defined $rename){
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if(defined $rename){
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open(FILE, ">$sw_path/$rename") || die "Can not open: $!";
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open(FILE, ">lib/verilog/tmp") || die "Can not open: $!";
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print FILE $content;
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print FILE $content;
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close(FILE) || die "Error closing file: $!";
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close(FILE) || die "Error closing file: $!";
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move ("$dir/lib/verilog/tmp","$sw_path/$rename");
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}
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}
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}
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}
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}
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}
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# Write Hardware gen files
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# Write Hardware gen files
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$rename=replace_golb_var($rename,\%params);
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$rename=replace_golb_var($rename,\%params);
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#read the file content
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#read the file content
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my $content=read_file_cntent($path,$project_dir);
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my $content=read_file_cntent($path,$project_dir);
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$content=replace_golb_var($content,\%params);
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$content=replace_golb_var($content,\%params);
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if(defined $rename){
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if(defined $rename){
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open(FILE, ">$hw_path/$rename") || die "Can not open: $!";
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open(FILE, ">lib/verilog/tmp") || die "Can not open: $!";
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print FILE $content;
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print FILE $content;
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close(FILE) || die "Error closing file: $!";
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close(FILE) || die "Error closing file: $!";
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move ("$dir/lib/verilog/tmp","$hw_path/$rename");
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}
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}
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}
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}
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}
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}
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}
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}
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add_text_to_string(\$system_h,"#endif\n");
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add_text_to_string(\$system_h,"#endif\n");
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my $name=$soc->object_get_attribute('soc_name');
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open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!";
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#write sytem.h file
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open(FILE, ">$sw_path/$name.h") || die "Can not open: $!";
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print FILE $system_h;
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print FILE $system_h;
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close(FILE) || die "Error closing file: $!";
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close(FILE) || die "Error closing file: $!";
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move ("$dir/lib/verilog/$name.h","$sw_path/");
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#write system.c file
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open(FILE, ">$sw_path/$name.c") || die "Can not open: $!";
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print FILE $system_c;
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close(FILE) || die "Error closing file: $!";
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}
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}
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