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URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [mpsoc_gen.pl] - Diff between revs 16 and 17

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Rev 16 Rev 17
Line 23... Line 23...
 
 
 
 
 
 
require "widget.pl";
require "widget.pl";
require "mpsoc_verilog_gen.pl";
require "mpsoc_verilog_gen.pl";
require "aeMB.pl";
require "hdr_file_gen.pl";
 
 
 
 
 
 
sub noc_param_widget{
sub noc_param_widget{
         my ($mpsoc,$name,$param, $default,$type,$content,$info, $state,$table,$row,$show)=@_;
         my ($mpsoc,$name,$param, $default,$type,$content,$info, $state,$table,$row,$show)=@_;
Line 239... Line 239...
 
 
}
}
 
 
sub get_conflict_decision{
sub get_conflict_decision{
        my ($mpsoc,$name,$inserted,$conflicts,$msg,$state)=@_;
        my ($mpsoc,$name,$inserted,$conflicts,$msg,$state)=@_;
        $msg="\tThe inserted tiles have been selected previously \"$msg\".\n \t Do u want to remove them for the current soc or from the previous ones? ";
        $msg="\tThe inserted tile number(s) have been mapped previously to \n\t\t\"$msg\".\n\tDo you want to remove the conflicted tiles number(s) in newly \n\tinsterd range or remove them from the previous ones? ";
 
 
        my $wind=def_popwin_size(100,300,"warning");
        my $wind=def_popwin_size(100,300,"warning");
        my $label= gen_label_in_left($msg);
        my $label= gen_label_in_left($msg);
        my $table=def_table(2,6,FALSE);
        my $table=def_table(2,6,FALSE);
        $table->attach_defaults ($label , 0, 6, 0,1);
        $table->attach_defaults ($label , 0, 6, 0,1);
Line 346... Line 346...
                if($p ne $name){
                if($p ne $name){
                        my @taken_tiles=$mpsoc->mpsoc_get_soc_tiles_num($p);
                        my @taken_tiles=$mpsoc->mpsoc_get_soc_tiles_num($p);
                        my @c=get_common_array(\@all_num,\@taken_tiles);
                        my @c=get_common_array(\@all_num,\@taken_tiles);
                        if (scalar @c) {
                        if (scalar @c) {
                                my $str=join(',', @c);
                                my $str=join(',', @c);
                                $conflicts_msg = (defined $conflicts_msg)? "$conflicts_msg, in $p:$str" : "in $p:$str";
                                $conflicts_msg = (defined $conflicts_msg)? "$conflicts_msg\n\t\t $str->$p" : "$str->$p";
                                @conflicts= (defined $conflicts_msg)? (@conflicts,@c): @c;
                                @conflicts= (defined $conflicts_msg)? (@conflicts,@c): @c;
                        }
                        }
                }#if
                }#if
        }
        }
        if (defined $conflicts_msg) {
        if (defined $conflicts_msg) {
Line 1146... Line 1146...
        mkpath("$target_dir/src_verilog/tiles/",1,0755);
        mkpath("$target_dir/src_verilog/tiles/",1,0755);
        mkpath("$target_dir/sw",1,0755);
        mkpath("$target_dir/sw",1,0755);
 
 
    #copy hdl codes in src_verilog
    #copy hdl codes in src_verilog
 
 
    my ($hdl_ref,$warnings)= get_all_hdl_files_list($soc);
    my ($hdl_ref,$warnings)= get_all_files_list($soc);
    foreach my $f(@{$hdl_ref}){
    foreach my $f(@{$hdl_ref}){
        my $n="$project_dir$f";
        my $n="$project_dir$f";
         if (-f "$n") {
         if (-f "$n") {
                        copy ("$n","$target_dir/src_verilog/lib");
                        copy ("$n","$target_dir/src_verilog/lib");
         }elsif(-f "$f" ){
         }elsif(-f "$f" ){
Line 1178... Line 1178...
                copy ("$dir/lib/verilog/$soc_name.v","$target_dir/src_verilog/tiles/");
                copy ("$dir/lib/verilog/$soc_name.v","$target_dir/src_verilog/tiles/");
                copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
                copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
 
 
 
 
                # Write header file
                # Write header file
                        my $file_h=aemb_generate_header($soc);
                        my $file_h=generate_header_file($soc);
                        open(FILE,  ">lib/verilog/$soc_name.h") || die "Can not open: $!";
                        open(FILE,  ">lib/verilog/$soc_name.h") || die "Can not open: $!";
                        print FILE $file_h;
                        print FILE $file_h;
                        close(FILE) || die "Error closing file: $!";
                        close(FILE) || die "Error closing file: $!";
 
 
 
 

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