| Line 87... |
Line 87... |
$min=~ s/\D//g;
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$min=~ s/\D//g;
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$max=~ s/\D//g;
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$max=~ s/\D//g;
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$step=~ s/\D//g;
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$step=~ s/\D//g;
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$widget=gen_spin($min,$max,$step);
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$widget=gen_spin($min,$max,$step);
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$widget->set_value($value);
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$widget->set_value($value);
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$widget-> signal_connect("changed" => sub{
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$widget-> signal_connect("value_changed" => sub{
|
my $new_param_value=$widget->get_value_as_int();
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my $new_param_value=$widget->get_value_as_int();
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$mpsoc->mpsoc_add_param($param,$new_param_value);
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$mpsoc->mpsoc_add_param($param,$new_param_value);
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set_state($state,"ref",1);
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set_state($state,"ref",1);
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|
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});
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});
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| Line 438... |
Line 438... |
$max=~ s/\D//g;
|
$max=~ s/\D//g;
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$step=~ s/\D//g;
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$step=~ s/\D//g;
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my $spin=gen_spin($min,$max,$step);
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my $spin=gen_spin($min,$max,$step);
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$spin->set_value($param_value{$p});
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$spin->set_value($param_value{$p});
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$table->attach_defaults ($spin, 3, 4, $row, $row+1);
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$table->attach_defaults ($spin, 3, 4, $row, $row+1);
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$spin-> signal_connect("changed" => sub{$param_value{$p}=$spin->get_value_as_int();});
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$spin-> signal_connect("value_changed" => sub{$param_value{$p}=$spin->get_value_as_int();});
|
|
|
# $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
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# $box=def_label_spin_help_box ($param,$info, $value,$min,$max,$step, 2);
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}
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}
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my $label =gen_label_in_center($p);
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my $label =gen_label_in_center($p);
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$table->attach_defaults ($label, 0, 3, $row, $row+1);
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$table->attach_defaults ($label, 0, 3, $row, $row+1);
|
| Line 1129... |
Line 1129... |
my @soc_list=$mpsoc-> mpsoc_get_soc_list();
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my @soc_list=$mpsoc-> mpsoc_get_soc_list();
|
my @used_socs;
|
my @used_socs;
|
foreach my $soc_name (@soc_list){
|
foreach my $soc_name (@soc_list){
|
my @n=$mpsoc->mpsoc_get_soc_tiles_num($soc_name);
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my @n=$mpsoc->mpsoc_get_soc_tiles_num($soc_name);
|
if(scalar @n){
|
if(scalar @n){
|
#this soc has been used generate the verilog files of it
|
#generate the verilog files of it
|
push(@used_socs,$soc_name);
|
push(@used_socs,$soc_name);
|
}
|
}
|
}
|
}
|
|
|
for my $p (@files){
|
for my $p (@files){
|
| Line 1220... |
Line 1220... |
move ("$dir/lib/verilog/$soc_name.v","$target_dir/src_verilog/tiles/");
|
move ("$dir/lib/verilog/$soc_name.v","$target_dir/src_verilog/tiles/");
|
copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
|
copy_noc_files($project_dir,"$target_dir/src_verilog/lib");
|
|
|
|
|
# Write header file
|
# Write header file
|
my $file_h=generate_header_file($soc);
|
generate_header_file($soc,$project_dir,$target_dir,$dir);
|
open(FILE, ">lib/verilog/$soc_name.h") || die "Can not open: $!";
|
|
print FILE $file_h;
|
|
close(FILE) || die "Error closing file: $!";
|
|
|
|
|
|
|
|
move ("$dir/lib/verilog/$soc_name.h","$target_dir/sw/");
|
|
|
|
#use File::Copy::Recursive qw(dircopy);
|
#use File::Copy::Recursive qw(dircopy);
|
#dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n");
|
#dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n");
|
|
|
|
|
