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Line 1... |
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use strict;
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use strict;
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use warnings;
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use warnings;
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use FindBin;
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use FindBin;
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use lib $FindBin::Bin;
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use lib $FindBin::Bin;
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use mpsoc;
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use mpsoc;
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use soc;
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use soc;
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| Line 12... |
Line 9... |
use ip_gen;
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use ip_gen;
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use Cwd;
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use Cwd;
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use rvp;
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use rvp;
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sub mpsoc_generate_verilog{
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sub mpsoc_generate_verilog{
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my ($mpsoc,$sw_dir)=@_;
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my ($mpsoc,$sw_dir,$txview)=@_;
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my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
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my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
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my $top_ip=ip_gen->top_gen_new();
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my $top_ip=ip_gen->top_gen_new();
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my $io_v="\tclk,\n\treset";
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#$top_ip->top_add_port($inst,$port,$range,$type,$intfc_name,$intfc_port);
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$top_ip->top_add_port('IO','reset','', 'input' ,'plug:reset[0]','reset_i');
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$top_ip->top_add_port('IO','clk','', 'input' ,'plug:clk[0]','clk_i');
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my $io_def_v="
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//IO
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\tinput\tclk,reset;\n";
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my $param_as_in_v;
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my $param_as_in_v;
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# generate top
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# generate top
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my $top_io="\t\t.clk(clk) ,\n\t\t.reset(reset_ored_jtag)";
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#generate socs_parameter
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#generate socs_parameter
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my $socs_param= gen_socs_param($mpsoc);
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my $socs_param= gen_socs_param($mpsoc);
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| Line 43... |
Line 32... |
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#generate the noc
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#generate the noc
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my $noc_v=gen_noc_v($mpsoc,$pass_param);
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my $noc_v=gen_noc_v($mpsoc,$pass_param);
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#generate socs
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#generate socs
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my $socs_v=gen_socs_v($mpsoc,\$io_v,\$io_def_v,\$top_io,$top_ip,$sw_dir);
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my ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,$href)=gen_socs_v($mpsoc,$top_ip,$sw_dir,$txview);
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my %jtag_info=%{$href};
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my $jtag_v=add_jtag_ctrl (\%jtag_info,$txview);
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my ($clk_set, $clk_io_sim,$clk_io_full, $clk_assigned_port)= get_top_clk_setting($mpsoc);
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$top_io_short=$top_io_short.",\n$clk_io_sim" if (defined $clk_io_sim);
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$top_io_full=$top_io_full."\n$clk_io_full";
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$top_io_pass=$top_io_pass.",\n$clk_assigned_port" if (defined $clk_assigned_port);
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#functions
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#functions
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my $functions=get_functions();
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my $functions=get_functions();
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my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name (\n$io_v\n);\n";
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my $global_localparam=get_golal_param_v();
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add_text_to_string (\$mpsoc_v,$noc_param);
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add_text_to_string (\$mpsoc_v,$functions);
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add_text_to_string (\$mpsoc_v,$socs_param);
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add_text_to_string (\$mpsoc_v,$io_def_v);
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add_text_to_string (\$mpsoc_v,$noc_v);
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add_text_to_string (\$mpsoc_v,$socs_v);
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add_text_to_string (\$mpsoc_v,"\nendmodule\n");
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my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$io_v\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $io_v\n);\n";
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add_text_to_string (\$top_v,$socs_param);
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add_text_to_string (\$top_v,$io_def_v);
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add_text_to_string(\$top_v,"
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// Allow software to remote reset/enable the cpu via jtag
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wire jtag_cpu_en, jtag_system_reset;
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my $mpsoc_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule $mpsoc_name\n\t import pronoc_pkg::*;\n\t #(\n $param_as_in_v\n)(\n$io_short\n);\n": "`timescale 1ns/1ps\nmodule $mpsoc_name\n \t import pronoc_pkg::*;\n\t(\n$io_short\n);\n";
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$mpsoc_v=$mpsoc_v. "
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$functions
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$global_localparam
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$socs_param
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$io_full
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$noc_v
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$socs_v
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endmodule
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";
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jtag_system_en jtag_en (
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.cpu_en(jtag_cpu_en),
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.system_reset(jtag_system_reset)
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);
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my $top_v = (defined $param_as_in_v )? "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top #(\n $param_as_in_v\n)(\n$top_io_short\n);\n": "`timescale 1ns/1ps\nmodule ${mpsoc_name}_top (\n $top_io_short\n);\n";
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wire reset_ored_jtag = reset | jtag_system_reset;
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$top_v=$top_v."
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wire processors_en_anded_jtag = processors_en & jtag_cpu_en;
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$global_localparam
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$socs_param
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$top_io_full
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$clk_set
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$jtag_v
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\t${mpsoc_name} the_${mpsoc_name} (
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$top_io_pass
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${mpsoc_name} the_${mpsoc_name} (
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\t);
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endmodule
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";
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$top_io
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);
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endmodule
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# my $mp=get_top_ip($mpsoc,'mpsoc');
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# mkpath("$dir/lib/ip/mpsoc/",1,01777);
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# open(FILE, ">$dir/lib/ip/mpsoc/MPSOC.IP") || die "Can not open: $!";
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# print FILE perl_file_header("MPSOC.IP");
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# print FILE Data::Dumper->Dump([\%$mp],["ipgen"]);
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# close(FILE) || die "Error closing file: $!";
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# my ($mp_v,$top_v)=soc_generate_verilog($top_soc,"target_dir/sw1",$txview);
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");
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#my $ins= gen_mpsoc_instance_v($mpsoc,$mpsoc_name,$param_pass_v);
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#my $ins= gen_mpsoc_instance_v($mpsoc,$mpsoc_name,$param_pass_v);
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#add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
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#add_text_to_string(\$top_v,$local_param_v_all."\n".$io_full_v_all);
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#add_text_to_string(\$top_v,$ins);
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#add_text_to_string(\$top_v,$ins);
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$mpsoc->object_add_attribute('top_ip',undef,$top_ip);
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$mpsoc->object_add_attribute('top_ip',undef,$top_ip);
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return ($mpsoc_v,$top_v);
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my @chains = (sort { $b <=> $a } keys %jtag_info);
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$mpsoc->object_add_attribute('JTAG','M_CHAIN',$chains[0]);
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return ($mpsoc_v,$top_v,$noc_param);
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}
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sub add_sources_to_top_ip{
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my ($mpsoc,$top_ip)=@_;
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my $sourc_short;
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my $source_full="";
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my @sources=('clk','reset');
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foreach my $s (@sources){
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my $num = $mpsoc->object_get_attribute('SOURCE_SET',"${s}_number");
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$num=1 if (!defined $num);
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for (my $n=0;$n<$num;$n++){
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my $name=$mpsoc->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
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$name=$s if(!defined $name);
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$top_ip->top_add_port('IO',$name,'', 'input' ,"plug:$s\[$n\]","${s}_i");
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$sourc_short= (defined $sourc_short)? $sourc_short.",\n\t$name" : "\t$name";
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#$source_full=$source_full. "// synthesis attribute keep of $name is true;\n" if($s eq 'clk');
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$source_full=$source_full."\tinput $name;\n";
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}
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#$top_ip->top_add_port('IO','clk','', 'input' ,'plug:clk[0]','clk_i');
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}
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return ($sourc_short, $source_full);
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}
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sub get_clk_constrain_file{
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my ($self)=@_;
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my $s='clk';
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my $num = $self->object_get_attribute('SOURCE_SET',"${s}_number");
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my $top_name=$self->object_get_attribute('mpsoc_name');
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$top_name=$self->object_get_attribute('soc_name') if(!defined $top_name);
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my $xdc="";
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return if (!defined $num);
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for (my $n=0;$n<$num;$n++){
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my $clk_name=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_name");
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my $period=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_period");
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my $fall=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_fall");
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my $rise=$self->object_get_attribute('SOURCE_SET',"${s}_${n}_rise");
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my $fal_ns= ($period * $fall)/100;
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my $rise_ns= ($period * $rise)/100;
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$xdc=$xdc."create_clock -period $period -name internal_clk$n -waveform {$rise_ns $fal_ns} -add \[get_nets uut/the_${top_name}/${clk_name}\]\n";
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}
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return $xdc;
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}
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sub add_jtag_ctrl {
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my ($ref,$txview)=@_;
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my %jtag_info=%{$ref};
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my $jtag_v="\t//Allow software to remote reset/enable the cpu via jtag
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\twire jtag_cpu_en, jtag_system_reset;
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";
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my @chains = (sort { $b <=> $a } keys %jtag_info);
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my $altera=0;
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my $xilinx=0;
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my $glob_en;
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foreach my $c (@chains){
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my $xilinx_jtag_ctrl_in;
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my $xilinx_jtag_ctrl_out;
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my $r = $jtag_info{$c}{'wire'};
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my $index = $jtag_info{$c}{'index'};
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my @array = (defined $r)? @{$r} :();
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my $wires_def = join ("\n",@array);
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$jtag_v=$jtag_v."\n//\tJtag chain $c Wire def\n$wires_def\n" if(@array);
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$r= $jtag_info{$c}{'altera_num'};
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@array = (defined $r)? @{$r} :();
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my $altera_jtag_ctrl =(@array)? scalar @array : 0;
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$r= $jtag_info{$c}{'xilinx_num'};
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@array = (defined $r)? @{$r} :();
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my $xilinx_jtag_ctrl =(@array)? scalar @array : 0;
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$altera+=$altera_jtag_ctrl;
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$xilinx+=$xilinx_jtag_ctrl;
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if ($xilinx_jtag_ctrl>0){
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$r=$jtag_info{$c}{'input'};
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@array = (defined $r)? @{$r} :();
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$xilinx_jtag_ctrl_in = ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
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$r=$jtag_info{$c}{'output'};
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@array = (defined $r)? @{$r} :();
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$xilinx_jtag_ctrl_out= ($xilinx_jtag_ctrl!=1)? '{'.join(',',@array).'}' : $array[0];
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my $ctrl = (defined $glob_en)? "
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.system_reset( ),
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.cpu_en( ),
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" : "//The global reset/enable signals are connected to the tap with the largest jtag chain number
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.system_reset(jtag_system_reset),
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.cpu_en(jtag_cpu_en),
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";
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$glob_en=1;
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$jtag_v=$jtag_v."
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xilinx_jtag_wb #(
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.JTAG_CHAIN($c),
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.JWB_NUM($xilinx_jtag_ctrl)
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)
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jwb_$c
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(
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$ctrl
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.reset(jtag_debug_reset_in),
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.wb_to_jtag_all($xilinx_jtag_ctrl_out),
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.jtag_to_wb_all($xilinx_jtag_ctrl_in)
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);
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";
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}
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}#for
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if($altera>0 && $xilinx>0){
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my $r = $jtag_info{0}{'inst'};
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my @array = (defined $r)? @{$r} :();
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my $inst=join ("\n\t",@array);
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add_colored_info($txview,"Found JTAG communication ports from different FPGA vendors:\n$inst.",'red');
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}
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elsif($altera>0){
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$jtag_v=$jtag_v."
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jtag_system_en #(
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.FPGA_VENDOR(\"ALTERA\")
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) jtag_en (
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.cpu_en(jtag_cpu_en),
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.system_reset(jtag_system_reset)
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);
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";
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}
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elsif($altera==0 && $xilinx==0){
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$jtag_v=$jtag_v."
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//No jtag connection has found in the design
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jtag_system_en #(
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.FPGA_VENDOR(FPGA_VENDOR)
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) jtag_en (
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.cpu_en(jtag_cpu_en),
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.system_reset(jtag_system_reset)
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);
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";
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}
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}
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return $jtag_v;
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}
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sub get_functions{
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sub get_functions{
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my $p='
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my $p='
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//functions
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//functions
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function integer log2;
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function integer log2;
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input integer number; begin
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input integer number; begin
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| Line 108... |
Line 268... |
log2=log2+1;
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log2=log2+1;
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end
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end
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end
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end
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endfunction // log2
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endfunction // log2
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';
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';
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return $p;
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return $p;
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}
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}
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sub gen_socs_param{
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sub gen_socs_param{
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my $mpsoc=shift;
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my $mpsoc=shift;
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| Line 131... |
Line 284... |
my $processors_en=0;
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my $processors_en=0;
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for (my $tile=0;$tile<$NE;$tile++){
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for (my $tile=0;$tile<$NE;$tile++){
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my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile);
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my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile);
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if(defined $soc_name) {
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if(defined $soc_name) {
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my $param= gen_soc_param($mpsoc,$soc_name,$soc_num,$tile);
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my $param= gen_soc_param($mpsoc,$soc_name,$soc_num,$tile);
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add_text_to_string(\$socs_param,$param);
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$socs_param=$socs_param.$param;
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}
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}
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}#$tile
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}#$tile
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$socs_param="$socs_param \n";
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$socs_param="$socs_param \n";
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return $socs_param;
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return $socs_param;
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}
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}
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sub gen_soc_param {
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sub gen_soc_param {
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my ($mpsoc,$soc_name,$soc_num,$tile)=@_;
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my ($mpsoc,$soc_name,$soc_num,$tile_num)=@_;
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my $top=$mpsoc->mpsoc_get_soc($soc_name);
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my $top=$mpsoc->mpsoc_get_soc($soc_name);
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my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile);
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my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
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my %params;
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my %params;
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if ($setting eq 'Custom'){
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#if ($setting eq 'Custom'){
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%params= $top->top_get_custom_soc_param($tile);
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%params= $top->top_get_custom_soc_param($tile_num);
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}else{
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#}else{
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%params=$top->top_get_default_soc_param();
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# %params=$top->top_get_default_soc_param();
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}
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#}
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my $params="\n\t //Parameter setting for $soc_name located in tile: $tile \n";
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my $params="\n\t //Parameter setting for $soc_name located in tile: $tile_num \n";
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foreach my $p (sort keys %params){
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$params{'CORE_ID'}=$tile_num;
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$params="$params\t localparam ${soc_name}_${soc_num}_$p=$params{$p};\n";
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foreach my $p (get_param_list_in_order(\%params)){
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}
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$params{$p}=add_instantc_name_to_parameters(\%params,"T$tile_num",$params{$p});
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$params="$params\t localparam T${tile_num}_$p=$params{$p};\n";
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}
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return $params;
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return $params;
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}
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}
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sub gen_noc_param_v{
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sub gen_noc_param_v{
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my $mpsoc=shift;
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my ($mpsoc,$sample)=@_;
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my $param_v="\n\n//NoC parameters\n";
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my $param_v="\n\n//NoC parameters\n";
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my $pass_param;
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my $pass_param="";
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my @params=$mpsoc->object_get_attribute_order('noc_param');
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my @params=$mpsoc->object_get_attribute_order('noc_param');
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my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
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my %noc_info;
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if(defined $sample ){
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my $ref=$mpsoc->object_get_attribute($sample,"noc_info");
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%noc_info= %$ref;
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}
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foreach my $p (@params){
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foreach my $p (@params){
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my $val=$mpsoc->object_get_attribute('noc_param',$p);
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add_text_to_string (\$param_v,"\tlocalparam $p=$val;\n");
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my $val= (defined $sample) ? $noc_info{$p} :$mpsoc->object_get_attribute('noc_param',$p);
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add_text_to_string (\$pass_param,".$p($p),\n");
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next if($p eq "CUSTOM_TOPOLOGY_NAME");
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$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
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$param_v= $param_v."\tlocalparam $p=$val;\n";
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$pass_param=$pass_param."\t\t.$p($p),\n";
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#print "$p:$val\n";
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#print "$p:$val\n";
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}
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}
|
my $class=$mpsoc->object_get_attribute('noc_param',"C");
|
my $class=$mpsoc->object_get_attribute('noc_param',"C");
|
my $str;
|
my $str;
|
if( $class > 1){
|
if( $class > 1){
|
for (my $i=0; $i<=$class-1; $i++){
|
for (my $i=0; $i<=$class-1; $i++){
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my $n="Cn_$i";
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my $n="Cn_$i";
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my $val=$mpsoc->object_get_attribute('class_param',$n);
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my $val=$mpsoc->object_get_attribute('class_param',$n);
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add_text_to_string (\$param_v,"\tlocalparam $n=$val;\n");
|
$param_v=$param_v."\tlocalparam $n=$val;\n";
|
}
|
}
|
$str="CLASS_SETTING={";
|
$str="CLASS_SETTING={";
|
for (my $i=$class-1; $i>=0;$i--){
|
for (my $i=$class-1; $i>=0;$i--){
|
$str=($i==0)? "${str}Cn_0};\n " : "${str}Cn_$i,";
|
$str=($i==0)? "${str}Cn_0};\n " : "${str}Cn_$i,";
|
}
|
}
|
}else {
|
}else {
|
$str="CLASS_SETTING={V{1\'b1}};\n";
|
$str="CLASS_SETTING={V{1\'b1}};\n";
|
}
|
}
|
add_text_to_string (\$param_v,"\tlocalparam $str");
|
$param_v=$param_v."\tlocalparam $str";
|
add_text_to_string (\$pass_param,".CLASS_SETTING(CLASS_SETTING),\n");
|
$pass_param=$pass_param."\t\t.CLASS_SETTING(CLASS_SETTING),\n";
|
my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
|
my $v=$mpsoc->object_get_attribute('noc_param',"V")-1;
|
my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
|
my $escape=$mpsoc->object_get_attribute('noc_param',"ESCAP_VC_MASK");
|
if (! defined $escape){
|
if (! defined $escape){
|
add_text_to_string (\$param_v,"\tlocalparam [$v :0] ESCAP_VC_MASK=1;\n");
|
$param_v=$param_v."\tlocalparam [$v :0] ESCAP_VC_MASK=1;\n";
|
add_text_to_string (\$pass_param,".ESCAP_VC_MASK(ESCAP_VC_MASK),\n");
|
$pass_param=$pass_param.".\t\tESCAP_VC_MASK(ESCAP_VC_MASK),\n";
|
}
|
}
|
add_text_to_string (\$param_v," \tlocalparam CVw=(C==0)? V : C * V;\n");
|
$param_v=$param_v." \tlocalparam CVw=(C==0)? V : C * V;\n";
|
add_text_to_string (\$pass_param,".CVw(CVw)\n");
|
$pass_param=$pass_param."\t\t.CVw(CVw)\n";
|
|
|
|
|
return ($param_v,$pass_param);
|
return ($param_v,$pass_param);
|
|
|
|
|
|
|
}
|
}
|
|
|
|
|
sub gen_noc_param_h{
|
sub gen_noc_param_h{
|
my $mpsoc=shift;
|
my $mpsoc=shift;
|
my $param_h="\n\n//NoC parameters\n";
|
my $param_h="\n\n//NoC parameters\n";
|
|
|
|
my $topology = $mpsoc->object_get_attribute('noc_param','TOPOLOGY');
|
|
$topology =~ s/"//g;
|
|
$param_h.="\t#define IS_${topology}\n";
|
|
|
|
|
my @params=$mpsoc->object_get_attribute_order('noc_param');
|
my @params=$mpsoc->object_get_attribute_order('noc_param');
|
|
my $custom_topology = $mpsoc->object_get_attribute('noc_param','CUSTOM_TOPOLOGY_NAME');
|
foreach my $p (@params){
|
foreach my $p (@params){
|
my $val=$mpsoc->object_get_attribute('noc_param',$p);
|
my $val=$mpsoc->object_get_attribute('noc_param',$p);
|
add_text_to_string (\$param_h,"\t#define $p\t$val\n");
|
next if($p eq "CUSTOM_TOPOLOGY_NAME");
|
|
$val=$custom_topology if($p eq "TOPOLOGY" && $val eq "\"CUSTOM\"");
|
|
$param_h=$param_h."\t#define $p\t$val\n";
|
|
|
#print "$p:$val\n";
|
#print "$p:$val\n";
|
|
|
}
|
}
|
my $class=$mpsoc->object_get_attribute('noc_param',"C");
|
my $class=$mpsoc->object_get_attribute('noc_param',"C");
|
my $str;
|
my $str;
|
if( $class > 1){
|
if( $class > 1){
|
for (my $i=0; $i<=$class-1; $i++){
|
for (my $i=0; $i<=$class-1; $i++){
|
my $n="Cn_$i";
|
my $n="Cn_$i";
|
my $val=$mpsoc->object_get_attribute('class_param',$n);
|
my $val=$mpsoc->object_get_attribute('class_param',$n);
|
add_text_to_string (\$param_h,"\t#define $n\t$val\n");
|
$param_h=$param_h."\t#define $n\t$val\n";
|
}
|
}
|
$str="CLASS_SETTING {";
|
$str="CLASS_SETTING {";
|
for (my $i=$class-1; $i>=0;$i--){
|
for (my $i=$class-1; $i>=0;$i--){
|
$str=($i==0)? "${str}Cn_0};\n " : "${str}Cn_$i,";
|
$str=($i==0)? "${str}Cn_0};\n " : "${str}Cn_$i,";
|
}
|
}
|
| Line 245... |
Line 413... |
}
|
}
|
#add_text_to_string (\$param_h," \tlocalparam CVw=(C==0)? V : C * V;\n");
|
#add_text_to_string (\$param_h," \tlocalparam CVw=(C==0)? V : C * V;\n");
|
#add_text_to_string (\$pass_param,".CVw(CVw)\n");
|
#add_text_to_string (\$pass_param,".CVw(CVw)\n");
|
|
|
|
|
return $param_h;
|
|
|
|
|
|
|
|
|
return $param_h;
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
sub gen_noc_v{
|
sub gen_noc_v{
|
my ($mpsoc,$pass_param) = @_;
|
my ($mpsoc,$pass_param) = @_;
|
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
|
my ($NE, $NR, $RAw, $EAw, $Fw) = get_topology_info($mpsoc);
|
my $noc = read_verilog_file("../src_noc/noc.v");
|
|
my @noc_param=$noc->get_modules_parameters_not_local_order('noc');
|
|
|
|
|
|
my $noc_v="
|
my $noc_clk = $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"NoC_clk");
|
|
my $noc_reset = $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"NoC_reset");
|
|
$noc_clk = 'clk0' if(!defined $noc_clk );
|
|
$noc_reset = 'reset0' if(!defined $noc_reset);
|
|
|
localparam
|
my $noc_v="
|
NE = $NE,
|
|
NR = $NR,
|
|
RAw = $RAw,
|
|
EAw = $EAw,
|
|
Fw = $Fw,
|
|
NEFw = NE * Fw,
|
|
NEV = NE * V;
|
|
|
|
//NoC ports
|
|
// connection to NI modules
|
|
wire [Fw-1 : 0] ni_flit_out [NE-1 :0];
|
|
wire [NE-1 : 0] ni_flit_out_wr;
|
|
wire [V-1 : 0] ni_credit_in [NE-1 :0];
|
|
wire [Fw-1 : 0] ni_flit_in [NE-1 :0];
|
|
wire [NE-1 : 0] ni_flit_in_wr;
|
|
wire [V-1 : 0] ni_credit_out [NE-1 :0];
|
|
|
|
//connection wire to NoC
|
//connection wire to NoC
|
wire [NEFw-1 : 0] flit_out_all;
|
smartflit_chanel_t ni_chan_in [NE-1 : 0];
|
wire [NE-1 : 0] flit_out_wr_all;
|
smartflit_chanel_t ni_chan_out [NE-1 : 0];
|
wire [NEV-1 : 0] credit_in_all;
|
|
wire [NEFw-1 : 0] flit_in_all;
|
|
wire [NE-1 : 0] flit_in_wr_all;
|
|
wire [NEV-1 : 0] credit_out_all;
|
|
|
|
wire noc_clk,noc_reset;
|
wire noc_clk_in,noc_reset_in;
|
";
|
|
|
|
|
//NoC
|
|
noc_top the_noc
|
|
(
|
|
.reset(noc_reset_in),
|
|
.clk(noc_clk_in),
|
|
.chan_in_all(ni_chan_out),
|
|
.chan_out_all(ni_chan_in)
|
|
);
|
|
|
|
|
|
|
$noc_v="$noc_v
|
|
//NoC\n \tnoc #(\n";
|
|
my $i=0;
|
|
foreach my $p (@noc_param){
|
|
my $param=($i==0)? "\t\t.$p($p)":",\n\t\t.$p($p)";
|
|
$i=1;
|
|
#add_text_to_string(\$noc_v,$param);
|
|
}
|
|
add_text_to_string(\$noc_v,"$pass_param\n\t)\n\tthe_noc\n\t(\n");
|
|
|
|
my @ports= $noc->get_module_ports_order('noc');
|
|
$i=0;
|
|
foreach my $p (@ports){
|
|
my $port;
|
|
if($p eq 'reset' ){
|
|
$port=($i==0)? "\t\t.$p(noc_reset)":",\n\t\t.$p(noc_reset)";
|
|
}elsif( $p eq 'clk'){
|
|
$port=($i==0)? "\t\t.$p(noc_clk)":",\n\t\t.$p(noc_clk)";
|
|
}else {
|
|
$port=($i==0)? "\t\t.$p($p)":",\n\t\t.$p($p)";
|
|
}
|
|
$i=1;
|
|
add_text_to_string(\$noc_v,$port);
|
|
}
|
|
add_text_to_string(\$noc_v,"\n\t);\n\n");
|
|
|
|
add_text_to_string(\$noc_v,'
|
|
clk_source src (
|
clk_source src (
|
.clk_in(clk),
|
.clk_in($noc_clk),
|
.clk_out(noc_clk),
|
.clk_out(noc_clk_in),
|
.reset_in(reset),
|
.reset_in($noc_reset),
|
.reset_out(noc_reset)
|
.reset_out(noc_reset_in)
|
);
|
);
|
');
|
";
|
|
|
|
|
|
;
|
|
return $noc_v;
|
|
|
|
}
|
|
|
add_text_to_string(\$noc_v,'
|
|
|
|
//NoC port assignment
|
|
genvar IP_NUM;
|
|
generate
|
|
for (IP_NUM=0; IP_NUM<NE; IP_NUM=IP_NUM+1) begin :endp
|
|
|
|
assign ni_flit_in [IP_NUM] = flit_out_all [(IP_NUM+1)*Fw-1 : IP_NUM*Fw];
|
|
assign ni_flit_in_wr [IP_NUM] = flit_out_wr_all [IP_NUM];
|
|
assign credit_in_all [(IP_NUM+1)*V-1 : IP_NUM*V] = ni_credit_out [IP_NUM];
|
|
assign flit_in_all [(IP_NUM+1)*Fw-1 : IP_NUM*Fw] = ni_flit_out [IP_NUM];
|
|
assign flit_in_wr_all [IP_NUM] = ni_flit_out_wr [IP_NUM];
|
|
assign ni_credit_in [IP_NUM] = credit_out_all [(IP_NUM+1)*V-1 : IP_NUM*V];
|
|
|
|
end
|
sub gen_socs_v{
|
endgenerate
|
my ($mpsoc,$top_ip,$sw_dir,$txview)=@_;
|
|
|
'
|
#add clk reset signals
|
);
|
my ($sourc_short, $source_full)=add_sources_to_top_ip($mpsoc,$top_ip);
|
return $noc_v;
|
|
|
|
}
|
|
|
|
|
my $io_short=$sourc_short;
|
|
my $top_io_short="\tjtag_debug_reset_in";
|
|
|
|
|
|
# my $jtag_def="// Allow software to remote reset/enable the cpu via jtag
|
|
#\twire jtag_cpu_en, jtag_system_reset;
|
|
#\twire processors_en_anded_jtag = processors_en & jtag_cpu_en;
|
|
#
|
|
#";
|
|
|
sub gen_socs_v{
|
my $io_full=$source_full;
|
my ($mpsoc,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_dir)=@_;
|
my $top_io_full= "\tinput jtag_debug_reset_in;\n";
|
|
my $top_io_pass="//";
|
|
|
|
my %jtag_info;
|
|
%jtag_info=append_to_hash (\%jtag_info,0,'wire',"wire processors_en_anded_jtag = processors_en & jtag_cpu_en;\n");
|
|
#my $altera_jtag_ctrl=0;
|
|
#my $xilinx_jtag_ctrl=0; #if it becomes larger than 0 then add jtag to wb module
|
|
#my $jtag_insts="";
|
|
#my $xilinx_jtag_ctrl_in="";
|
|
#my $xilinx_jtag_ctrl_out="";
|
|
|
|
|
my $socs_v;
|
my $socs_v="";
|
my ($NE, $NR, $RAw, $EAw, $EYw)= get_topology_info ($mpsoc);
|
my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc);
|
|
|
|
|
my $processors_en=0;
|
my $processors_en=0;
|
for (my $id=0;$id<$NE;$id++){
|
for (my $tile_num=0;$tile_num<$NE;$tile_num++){
|
my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($id);
|
my ($soc_name,$n,$soc_num)=$mpsoc->mpsoc_get_tile_soc_name($tile_num);
|
|
|
if(defined $soc_name) {
|
if(defined $soc_name) {
|
my ($soc_v,$en)= gen_soc_v($mpsoc,$soc_name,$id,$soc_num,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_dir);
|
my ($soc_v,$en,$io_short1,$io_full1,$top_io_short1,$top_io_full1,$top_io_pass1,$ref)=
|
add_text_to_string(\$socs_v,$soc_v);
|
gen_soc_v($mpsoc,$top_ip,$sw_dir,$soc_name,$tile_num,$soc_num,$txview,\%jtag_info);
|
|
%jtag_info=%{$ref};
|
|
$socs_v=$socs_v.$soc_v;
|
|
$io_short = $io_short .$io_short1;
|
|
$io_full = $io_full .$io_full1;
|
|
$top_io_short= $top_io_short.$top_io_short1;
|
|
$top_io_full = $top_io_full. $top_io_full1;
|
|
$top_io_pass = $top_io_pass. $top_io_pass1;
|
|
# $jtag_def = $jtag_def .$jtag_def1;
|
|
# $jtag_insts=$jtag_insts.$jtag_insts1;
|
|
# $altera_jtag_ctrl+=$altera_jtag_ctrl1;
|
|
# $xilinx_jtag_ctrl+=$xilinx_jtag_ctrl1;
|
|
# $xilinx_jtag_ctrl_in =(length ($xilinx_jtag_ctrl_in )>2)? "$xilinx_jtag_ctrl_in,$xilinx_jtag_ctrl_in1" : $xilinx_jtag_ctrl_in.$xilinx_jtag_ctrl_in1;
|
|
# $xilinx_jtag_ctrl_out=(length ($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$xilinx_jtag_ctrl_out1" :$xilinx_jtag_ctrl_out.$xilinx_jtag_ctrl_out1;
|
|
|
$processors_en|=$en;
|
$processors_en|=$en;
|
|
|
}else{
|
}else{
|
#this tile is not connected to any ip. the noc input ports will be connected to ground
|
#this tile is not connected to any ip. the noc input ports will be connected to ground
|
my $soc_v="\n\n // Tile:$id is not assigned to any ip\n";
|
my $soc_v="\n\n // Tile:$tile_num is not assigned to any ip\n";
|
$soc_v="$soc_v
|
$soc_v="$soc_v
|
|
|
assign ni_credit_out[$id]={V{1'b0}};
|
assign ni_credit_out[$tile_num]={V{1'b0}};
|
assign ni_flit_out[$id]={Fw{1'b0}};
|
assign ni_flit_out[$tile_num]={Fw{1'b0}};
|
assign ni_flit_out_wr[$id]=1'b0;
|
assign ni_flit_out_wr[$tile_num]=1'b0;
|
";
|
";
|
add_text_to_string(\$socs_v,$soc_v);
|
$socs_v=$socs_v.$soc_v;
|
|
|
}
|
}
|
|
|
}
|
}
|
|
|
if($processors_en){
|
if($processors_en){
|
add_text_to_string($io_v_ref,",\n\tprocessors_en");
|
$io_short=$io_short.",\n\tprocessors_en";
|
add_text_to_string($io_def_v,"\t input processors_en;");
|
$io_full=$io_full."\tinput processors_en;";
|
add_text_to_string($top_io_ref,",\n\t\t.processors_en(processors_en_anded_jtag)");
|
$top_io_short=$top_io_short.",\n\tprocessors_en";
|
|
$top_io_full=$top_io_full."\t input processors_en;";
|
|
$top_io_pass=$top_io_pass.",\n\t\t.processors_en(processors_en_anded_jtag)";
|
$top_ip->top_add_port('IO','processors_en','' ,'input','plug:enable[0]','enable_i');
|
$top_ip->top_add_port('IO','processors_en','' ,'input','plug:enable[0]','enable_i');
|
|
|
}
|
}
|
|
|
|
# $io_short=$io_short.",\n\tjtag_system_reset";
|
|
# $io_full=$io_full."\n\tinput jtag_system_reset;";
|
|
# $top_io_pass=$top_io_pass.",\n\t\t.jtag_system_reset(jtag_system_reset)";
|
|
|
return $socs_v;
|
|
|
return ($socs_v,$io_short,$io_full,$top_io_short,$top_io_full,$top_io_pass,\%jtag_info);
|
|
|
}
|
}
|
|
|
|
|
|
|
##############
|
##############
|
# gen_soc_v
|
# gen_soc_v
|
##############
|
##############
|
|
|
|
|
|
#$mpsoc,$top_ip,$sw_dir,$soc_name,$id,$soc_num,$txview
|
sub gen_soc_v{
|
sub gen_soc_v{
|
my ($mpsoc,$soc_name,$tile_num,$soc_num,$io_v_ref,$io_def_v,$top_io_ref,$top_ip,$sw_path)=@_;
|
my ($mpsoc,$top_ip,$sw_path,$soc_name,$tile_num,$soc_num,$txview,$href)=@_;
|
my $soc_v;
|
my %jtag_info = %{$href};
|
|
|
|
my $io_short="";
|
|
my $io_full="";
|
|
my $top_io_short="";
|
|
my $top_io_full="";
|
|
my $top_io_pass="";
|
|
|
|
|
|
|
my $processor_en=0;
|
my $processor_en=0;
|
|
|
|
|
|
|
|
|
|
|
my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc);
|
my ($NE, $NR, $RAw, $EAw, $Fw)= get_topology_info ($mpsoc);
|
my $e_addr=endp_addr_encoder($mpsoc,$tile_num);
|
my $e_addr=endp_addr_encoder($mpsoc,$tile_num);
|
my $router_num = get_connected_router_id_to_endp($mpsoc,$tile_num);
|
my $router_num = get_connected_router_id_to_endp($mpsoc,$tile_num);
|
my $r_addr=router_addr_encoder($mpsoc,$router_num);
|
my $r_addr=router_addr_encoder($mpsoc,$router_num);
|
|
|
|
|
|
|
$soc_v="\n\n // Tile:$tile_num ($e_addr)\n \t$soc_name #(\n";
|
my $soc_v="\n\n // Tile:$tile_num ($e_addr)\n \t$soc_name #(\n";
|
|
|
# Global parameter
|
# Global parameter
|
add_text_to_string(\$soc_v,"\t\t.CORE_ID($tile_num),\n\t\t.SW_LOC(\"$sw_path/tile$tile_num\")");
|
$soc_v=$soc_v."\t\t.CORE_ID($tile_num),\n\t\t.SW_LOC(\"$sw_path/tile$tile_num\")";
|
|
|
|
|
# ni parameter
|
# ni parameter
|
my $top=$mpsoc->mpsoc_get_soc($soc_name);
|
my $top=$mpsoc->mpsoc_get_soc($soc_name);
|
my @nis=get_NI_instance_list($top);
|
my @nis=get_NI_instance_list($top);
|
| Line 445... |
Line 613... |
|
|
foreach my $p (@noc_param){
|
foreach my $p (@noc_param){
|
my $parm_next = $p;
|
my $parm_next = $p;
|
$parm_next =~ s/${inst_name}_//;
|
$parm_next =~ s/${inst_name}_//;
|
my $param= ",\n\t\t.$p($parm_next)";
|
my $param= ",\n\t\t.$p($parm_next)";
|
add_text_to_string(\$soc_v,$param);
|
$soc_v=$soc_v.$param;
|
}
|
}
|
foreach my $p (sort keys %params){
|
foreach my $p (sort keys %params){
|
my $parm_next= "${soc_name}_${soc_num}_$p";
|
my $parm_next= "T${tile_num}_$p";
|
my $param= ",\n\t\t.$p($parm_next)";
|
my $param= ",\n\t\t.$p($parm_next)";
|
add_text_to_string(\$soc_v,$param);
|
$soc_v=$soc_v.$param;
|
|
|
}
|
}
|
|
|
add_text_to_string(\$soc_v,"\n\t)the_${soc_name}_$soc_num(\n");
|
$soc_v=$soc_v."\n\t)the_${soc_name}_$soc_num(\n";
|
|
|
my @intfcs=$top->top_get_intfc_list();
|
my @intfcs=$top->top_get_intfc_list();
|
|
|
my $i=0;
|
my $i=0;
|
|
|
my $dir = Cwd::getcwd();
|
my $dir = Cwd::getcwd();
|
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $mpsoc_name=$mpsoc->object_get_attribute('mpsoc_name');
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
|
my $target_dir = "$ENV{'PRONOC_WORK'}/MPSOC/$mpsoc_name";
|
my $soc_file="$target_dir/src_verilog/tiles/$soc_name.v";
|
my $soc_file="$target_dir/src_verilog/tiles/$soc_name.sv";
|
|
|
my $vdb =read_verilog_file($soc_file);
|
my $vdb =read_verilog_file($soc_file);
|
|
|
my %soc_localparam = $vdb->get_modules_parameters($soc_name);
|
my %soc_localparam = $vdb->get_modules_parameters($soc_name);
|
|
|
| Line 481... |
Line 649... |
foreach my $p (@ports){
|
foreach my $p (@ports){
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
my $q= ($intfc_port eq "current_e_addr")? "$EAw\'d$e_addr" :
|
my $q= ($intfc_port eq "current_e_addr")? "$EAw\'d$e_addr" :
|
($intfc_port eq "current_r_addr")? "$RAw\'d$r_addr" :
|
($intfc_port eq "current_r_addr")? "$RAw\'d$r_addr" :
|
"ni_$intfc_port\[$tile_num\]";
|
"ni_$intfc_port\[$tile_num\]";
|
add_text_to_string(\$soc_v,',') if ($i);
|
$soc_v=$soc_v.',' if ($i);
|
add_text_to_string(\$soc_v,"\n\t\t.$p($q)");
|
$soc_v=$soc_v."\n\t\t.$p($q)";
|
$i=1;
|
$i=1;
|
|
|
|
|
}
|
}
|
}
|
}
|
# clk source
|
# clk source
|
elsif( $intfc eq 'plug:clk[0]'){
|
elsif( $intfc =~ /plug:clk\[/ ){
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
foreach my $p (@ports){
|
foreach my $p (@ports){
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
add_text_to_string(\$soc_v,',') if ($i);
|
$soc_v=$soc_v.',' if ($i);
|
add_text_to_string(\$soc_v,"\n\t\t.$p(clk)");
|
my $src = $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");
|
|
$src = 'clk0' if(!defined $src);
|
|
$soc_v=$soc_v."\n\t\t.$p($src)";
|
$i=1;
|
$i=1;
|
|
|
}
|
}
|
}
|
}
|
#reset
|
#reset
|
elsif( $intfc eq 'plug:reset[0]'){
|
elsif( $intfc =~ /plug:reset\[/){
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
foreach my $p (@ports){
|
foreach my $p (@ports){
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
add_text_to_string(\$soc_v,',') if ($i);
|
$soc_v=$soc_v.',' if ($i);
|
add_text_to_string(\$soc_v,"\n\t\t.$p(reset)");
|
my $src = $mpsoc->object_get_attribute('SOURCE_SET_CONNECT',"T${tile_num}_$p");
|
|
$src = 'reset0' if(!defined $src);
|
|
$soc_v=$soc_v."\n\t\t.$p(${src} )";#| jtag_system_reset)";
|
$i=1;
|
$i=1;
|
|
|
}
|
}
|
|
|
|
|
|
|
}
|
}
|
#enable
|
#enable
|
elsif( $intfc eq 'plug:enable[0]'){
|
elsif( $intfc =~ /plug:enable\[/){
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
foreach my $p (@ports){
|
foreach my $p (@ports){
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
add_text_to_string(\$soc_v,',') if ($i);
|
$soc_v=$soc_v.',' if ($i);
|
add_text_to_string(\$soc_v,"\n\t\t.$p(processors_en)");
|
$soc_v=$soc_v."\n\t\t.$p(processors_en)";
|
$processor_en=1;
|
$processor_en=1;
|
$i=1;
|
$i=1;
|
|
|
}
|
}
|
|
|
|
|
}
|
}
|
#RxD_sim
|
#RxD_sim
|
elsif( $intfc eq 'socket:RxD_sim[0]'){
|
elsif( $intfc eq 'socket:RxD_sim[0]'){
|
#This interface is for simulation only donot include it in top module
|
#This interface is for simulation only donot include it in top module
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
foreach my $p (@ports){
|
foreach my $p (@ports){
|
add_text_to_string(\$soc_v,',') if ($i);
|
$soc_v=$soc_v.',' if ($i);
|
add_text_to_string(\$soc_v,"\n\t\t.$p( )");
|
$soc_v=$soc_v."\n\t\t.$p( )";
|
$i=1;
|
$i=1;
|
}
|
}
|
|
|
}
|
}
|
|
#jtag_to_wb
|
else {
|
elsif( $intfc =~ /socket:jtag_to_wb\[/){ #check JTAG connect parameter. if it is XILINX then connect it to jtag tap
|
#other interface
|
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
foreach my $p (@ports){
|
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
|
my $io_port="${soc_name}_${soc_num}_${p}";
|
|
#resolve range parameter
|
|
if (defined $range ){
|
|
my @a= split (/\b/,$range);
|
|
foreach my $l (@a){
|
|
#if defined in parameter list ignore it
|
|
next if(defined $params{$l});
|
|
($range=$range)=~ s/\b$l\b/$soc_localparam{$l}/g if(defined $soc_localparam{$l});
|
|
#else s
|
|
|
|
#print "$l\n";
|
my $setting=$mpsoc->mpsoc_get_tile_param_setting($tile_num);
|
}
|
my %topparams;
|
|
#if ($setting eq 'Custom'){
|
|
%topparams= $top->top_get_custom_soc_param($tile_num);
|
|
# }else{
|
|
# %topparams=$top->top_get_default_soc_param();
|
|
#}
|
|
|
}
|
|
#io name
|
|
add_text_to_string($io_v_ref,",\n\t$io_port");
|
|
add_text_to_string($top_io_ref,",\n\t\t.$io_port($io_port)");
|
|
#io definition
|
|
my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
|
|
#my $new_range=$range;
|
|
my $port_def=(length ($range)>1 )? "\t$type\t [ $new_range ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
|
|
$top_ip->top_add_port("${soc_name}_$tile_num" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
|
|
|
|
add_text_to_string($io_def_v,"$port_def");
|
|
add_text_to_string(\$soc_v,',') if ($i);
|
|
add_text_to_string(\$soc_v,"\n\t\t.$p($io_port)");
|
|
$i=1;
|
|
|
|
}
|
#my $JTAG_CONNECT=$soc->soc_get_module_param_value ($id,'JTAG_CONNECT');
|
|
|
|
foreach my $p (@ports){
|
|
my($id,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($p);
|
|
my $inst_name=$top->top_get_def_of_instance($id,'instance');
|
|
my $JTAG_CONNECT= $topparams{"${inst_name}_JTAG_CONNECT"};
|
|
my $chain=$topparams{"${inst_name}_JTAG_CHAIN"};
|
|
my $index=$topparams{"${inst_name}_JTAG_INDEX"};
|
|
#print Dumper (\%topparams);
|
|
#print "my $JTAG_CONNECT= \$topparams{${inst_name}_JTAG_CONNECT}\n";
|
|
|
|
#print "$inst,$range,$type,$intfc_name,$intfc_port-> $JTAG_CONNECT;";
|
|
if($JTAG_CONNECT =~ /XILINX_JTAG_WB/){
|
|
|
|
my ($io_port,$type,$new_range,$intfc_name,$intfc_port)= get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
|
|
my $port_def=(length ($new_range)>1 )? "\t$type\t [ $new_range ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
|
|
$top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
|
|
|
|
my $wire_def=(length ($new_range)>1 )? "\twire\t [ $new_range ] $io_port;": "\twire\t\t\t$io_port;";
|
|
# my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
|
|
|
}
|
# $jtag_def=$jtag_def."$wire_def";
|
|
%jtag_info=append_to_hash (\%jtag_info,$chain,'wire',"$wire_def");
|
|
|
|
|
|
$soc_v=$soc_v.',' if ($i);
|
|
$soc_v=$soc_v."\n\t\t.$p($io_port)";
|
|
$i=1;
|
|
if($type eq 'input'){
|
|
%jtag_info=check_jtag_indexs(\%jtag_info,$chain,$index,$txview,$inst_name,$tile_num);
|
|
#$jtag_insts=$jtag_insts."$id XILINX JTAG,";
|
|
%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id XILINX JTAG");
|
|
#$xilinx_jtag_ctrl++;
|
|
%jtag_info=append_to_hash (\%jtag_info,$chain,'xilinx_num',1);
|
|
#$xilinx_jtag_ctrl_in=(length ($xilinx_jtag_ctrl_in)>2)? "$xilinx_jtag_ctrl_in,$io_port" : "$io_port";
|
|
%jtag_info=append_to_hash (\%jtag_info,$chain,'input',$io_port);
|
|
}else {
|
|
#$xilinx_jtag_ctrl_out=(length($xilinx_jtag_ctrl_out)>2)? "$xilinx_jtag_ctrl_out,$io_port" : "$io_port";
|
|
%jtag_info=append_to_hash (\%jtag_info,$chain,'output',$io_port);
|
|
}
|
|
$io_short=$io_short.",\n\t$io_port";
|
|
$io_full=$io_full."$port_def";
|
|
$top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
|
|
#
|
|
}else{#Dont not connect
|
|
$soc_v=$soc_v.',' if ($i);
|
|
$soc_v=$soc_v."\n\t\t.$p( )";
|
|
$i=1;
|
}
|
}
|
|
|
add_text_to_string(\$soc_v,"\n\t);\n");
|
if($JTAG_CONNECT =~ /ALTERA_JTAG_WB/){
|
|
if($type eq 'input'){
|
|
#$jtag_insts=$jtag_insts."$id ALTERA JTAG,";
|
|
#$altera_jtag_ctrl++;
|
|
%jtag_info=append_to_hash (\%jtag_info,0,'inst',"$id ALTERA JTAG");
|
|
%jtag_info=append_to_hash (\%jtag_info,0,'altera_num',1);
|
|
%jtag_info=check_jtag_indexs(\%jtag_info,0,$index,$txview,$inst_name,$tile_num);
|
|
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
#other interface
|
|
my @ports=$top->top_get_intfc_ports_list($intfc);
|
|
foreach my $p (@ports){
|
|
my ($io_port,$type,$new_range,$intfc_name,$intfc_port)= get_top_port_io_info($top,$p,$tile_num,\%params,\%soc_localparam);
|
|
|
return ($soc_v,$processor_en);
|
$io_short=$io_short.",\n\t$io_port";
|
|
$top_io_short=$top_io_short.",\n\t$io_port";
|
|
$top_io_pass=$top_io_pass.",\n\t\t.$io_port($io_port)";
|
|
#io definition
|
|
#my $new_range = add_instantc_name_to_parameters(\%params,"${soc_name}_$soc_num",$range);
|
|
my $port_def=(length ($new_range)>1 )? "\t$type\t [ $new_range ] $io_port;\n": "\t$type\t\t\t$io_port;\n";
|
|
$top_ip->top_add_port("T${tile_num}" ,$io_port, $new_range ,$type,$intfc_name,$intfc_port);
|
|
|
|
$io_full=$io_full."$port_def";
|
|
$top_io_full=$top_io_full."$port_def";
|
|
$soc_v=$soc_v.',' if ($i);
|
|
$soc_v=$soc_v."\n\t\t.$p($io_port)";
|
|
$i=1;
|
|
|
}
|
}
|
|
|
|
|
sub log2{
|
|
my $num=shift;
|
|
my $log=0;
|
|
while( (1<< $log) < $num) {
|
|
$log++;
|
|
}
|
}
|
return $log;
|
|
}
|
}
|
|
|
|
|
|
|
sub gen_emulate_top_v{
|
$soc_v=$soc_v."\n\t);\n";
|
my $emulate=shift;
|
|
my ($localparam, $pass_param)=gen_noc_param_v( $emulate);
|
|
my $top_v="
|
|
|
|
module emulator_top (
|
|
output [0:0]LEDR,
|
|
output [0:0]LEDG,
|
|
input [0:0]KEY,
|
|
input CLOCK_50
|
|
);
|
|
|
|
|
|
|
|
|
return ($soc_v,$processor_en,$io_short,$io_full,$top_io_short, $top_io_full,$top_io_pass,\%jtag_info);
|
|
|
$localparam
|
}
|
|
|
|
|
wire reset_in,jtag_reset,reset,reset_sync;
|
|
|
|
assign reset_in = ~KEY[0];
|
sub check_jtag_indexs{
|
assign LEDG[0] = reset;
|
my ($ref,$chain,$index,$txview,$inst_name,$core_id)=@_;
|
assign reset = (jtag_reset | reset_in);
|
my %jtag_info = %{$ref} if (defined $ref);
|
wire done;
|
|
reg[31:0]time_cnt;
|
|
|
|
// a reset source which can be controled using jtag
|
|
jtag_source_probe #(
|
|
.VJTAG_INDEX(127),
|
|
.Dw(1) //source/probe width in bits
|
|
)the_reset(
|
|
.probe(done),
|
|
.source(jtag_reset)
|
|
);
|
|
|
|
altera_reset_synchronizer rst_sync
|
chomp $index;
|
(
|
# replace coreid parameter
|
.reset_in(reset),
|
($index=$index)=~ s/CORE_ID/$core_id/g;
|
.clk(CLOCK_50),
|
$index = eval $index;
|
.reset_out(reset_sync)
|
my $inst1 =$jtag_info{$chain}{'index'}{$index};
|
);
|
my $id1 = $jtag_info{$chain}{'core_id'}{$index};
|
|
if (defined $inst1){
|
|
add_colored_info($txview,"Error: The JTAG INDEX number $index in JTAG Chain $chain is not unique. The same index number is used in tile($id1):$inst1 & tile($core_id):$inst_name IPs. It should be used in only one module.\n",'red');
|
|
}
|
|
$jtag_info{$chain}{'index'}{$index}=$inst_name;
|
|
$jtag_info{$chain}{'core_id'}{$index}=$core_id;
|
|
#print "\$jtag_info{$chain}{'index'}{$index}=$inst_name\n";
|
|
return %jtag_info;
|
|
}
|
|
|
|
|
|
|
noc_emulator #(
|
sub get_top_clk_setting{
|
$pass_param
|
my $mpsoc=shift;
|
|
#get mpsoc with clock setting interface
|
|
my $dir = Cwd::getcwd();
|
|
my $soc =get_source_set_top($mpsoc);
|
|
|
// simulation
|
my @instances=$soc->soc_get_all_instances();
|
// parameter MAX_PCK_NUM=2560000,
|
my $top_ip=ip_gen->top_gen_new();
|
// parameter MAX_SIM_CLKs=1000000,
|
my $body_v;
|
// parameter MAX_PCK_SIZ=10,
|
my $param_pass_v="";
|
// parameter TIMSTMP_FIFO_NUM=16
|
my $io_sim_v;
|
)
|
my $io_top_sim_v;
|
emulate_top
|
my $core_id= 0 ;
|
(
|
my $param_as_in_v="";
|
.reset(reset_sync),
|
my $local_param_v_all="";
|
.clk(CLOCK_50),
|
my $inst_v_all="";
|
.done(done)
|
my $param_v_all="";
|
);
|
my $wire_def_v_all="";
|
|
my $plugs_assign_v_all="";
|
|
my $sockets_assign_v_all="";
|
|
my $io_full_v_all="";
|
|
my $io_top_full_v_all="";
|
|
my $io_sim_v_all;
|
|
my $system_v_all="";
|
|
|
|
my $wires=soc->new_wires();
|
|
my $intfc=interface->interface_new();
|
|
my $clk_assigned_port;
|
|
foreach my $id (@instances){
|
|
my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$io_sim_v,
|
|
$top_io_short,$param_as_in_v,$param_pass_v,$system_v,$assigned_ports,$top_io_pass,$src_io_short, $src_io_full)=gen_module_inst($id,$soc,$top_ip,$intfc,$wires);
|
|
|
|
#my ($param_v, $local_param_v, $wire_def_v, $inst_v, $plugs_assign_v, $sockets_assign_v,$io_full_v,$io_top_full_v,$system_v,$assigned_ports)=gen_module_inst($id,$soc,\$io_sim_v,\$io_top_sim_v,\$param_as_in_v,$top_ip,$intfc,$wires,\$param_pass_v,\$system_v);
|
|
my $inst = $soc->soc_get_instance_name($id);
|
|
if ($id ne 'TOP'){
|
|
add_text_to_string(\$body_v,"/*******************\n*\n*\t$inst\n*\n*\n*********************/\n");
|
|
add_text_to_string(\$system_v_all,"$system_v\n") if(defined($system_v));
|
|
add_text_to_string(\$local_param_v_all,"$local_param_v\n") if(defined($local_param_v));
|
|
add_text_to_string(\$wire_def_v_all,"$wire_def_v\n") if(defined($wire_def_v));
|
|
add_text_to_string(\$inst_v_all,$inst_v) if(defined($inst_v));
|
|
add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") if(defined($plugs_assign_v));
|
|
add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
|
|
add_text_to_string(\$io_full_v_all,"$io_full_v\n") if(length($io_full_v)>3);
|
|
add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n") if(length($io_top_full_v)>3);
|
|
$io_sim_v_all = (defined $io_sim_v_all )? "$io_sim_v_all,\n$io_sim_v" : $io_sim_v if(defined($io_sim_v));
|
|
}else{
|
|
add_text_to_string(\$system_v_all,"$system_v\n") if(defined($system_v));
|
|
add_text_to_string(\$wire_def_v_all,"$wire_def_v\n") if(defined($wire_def_v));
|
|
add_text_to_string(\$plugs_assign_v_all,"$plugs_assign_v\n") if(defined($plugs_assign_v));
|
|
add_text_to_string(\$sockets_assign_v_all,"$sockets_assign_v\n")if(defined($sockets_assign_v));
|
|
add_text_to_string(\$io_full_v_all,"$io_full_v\n") if(length($io_full_v)>3);
|
|
$io_sim_v_all = (defined $io_sim_v_all )? "$io_sim_v_all,\n$io_sim_v" : $io_sim_v if(defined($io_sim_v));
|
|
add_text_to_string(\$io_top_full_v_all,"$io_top_full_v\n") if(length($io_top_full_v)>3);
|
|
$clk_assigned_port= (defined $clk_assigned_port)? "$clk_assigned_port,\n$assigned_ports" : $assigned_ports if(defined $assigned_ports);
|
|
}
|
|
|
|
}
|
|
|
jtag_source_probe #(
|
|
.VJTAG_INDEX(126),
|
|
.Dw(32) //source/probe width in bits
|
|
|
|
|
|
)
|
|
src_pb
|
|
(
|
|
.probe(time_cnt),
|
|
.source()
|
|
);
|
|
|
|
|
|
always @(posedge CLOCK_50 or posedge reset)begin
|
|
if(reset) begin
|
|
time_cnt<=0;
|
|
end else begin
|
|
if(!done) time_cnt<=time_cnt+1;
|
|
end
|
|
end
|
|
|
|
|
my $unused_wiers_v=assign_unconnected_wires($wires,$intfc);
|
|
$unused_wiers_v= "" if(!defined $unused_wiers_v);
|
|
|
|
my $soc_v = "
|
|
$system_v_all
|
|
$local_param_v_all
|
|
$wire_def_v_all
|
|
$unused_wiers_v
|
|
$inst_v_all
|
|
$plugs_assign_v_all
|
|
$sockets_assign_v_all
|
|
|
assign LEDR[0]=done;
|
";
|
|
my $clk_io_full= $io_full_v_all;
|
|
my $clk_io_sim=$io_sim_v_all;
|
|
return ($soc_v,$clk_io_sim,$clk_io_full,$clk_assigned_port);
|
|
|
|
}
|
|
|
endmodule
|
sub get_top_port_io_info{
|
|
my ($top,$port,$tile_num,$params_ref,$local_param_ref)=@_;
|
|
my %params =%{$params_ref} if(defined $params_ref);
|
|
my %localparams=%{$local_param_ref} if(defined $local_param_ref);
|
|
my($inst,$range,$type,$intfc_name,$intfc_port)= $top->top_get_port($port);
|
|
my $io_port="T${tile_num}_${port}";
|
|
#resolve range parameter
|
|
if (defined $range ){
|
|
my @a= split (/\b/,$range);
|
|
foreach my $l (@a){
|
|
#if defined in parameter list ignore it
|
|
next if(defined $params{$l});
|
|
($range=$range)=~ s/\b$l\b/$localparams{$l}/g if(defined $localparams{$l});
|
|
}
|
|
}
|
|
my $new_range = add_instantc_name_to_parameters(\%params,"T${tile_num}",$range);
|
|
return ($io_port,$type,$new_range,$intfc_name,$intfc_port);
|
|
}
|
|
|
|
|
";
|
|
return $top_v;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
1
|
1
|
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No newline at end of file
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No newline at end of file
|
