| Line 8... |
Line 8... |
use POSIX 'strtol';
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use POSIX 'strtol';
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use File::Path;
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use File::Path;
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use File::Find;
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use File::Find;
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use File::Copy;
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use File::Copy;
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use File::Copy::Recursive qw(dircopy);
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use Cwd 'abs_path';
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use Cwd 'abs_path';
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use Gtk2;
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use Gtk2;
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use Gtk2::Pango;
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use Gtk2::Pango;
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| Line 27... |
Line 27... |
use constant NUM_COLUMNS => 4;
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use constant NUM_COLUMNS => 4;
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require "widget.pl";
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require "widget.pl";
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require "verilog_gen.pl";
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require "verilog_gen.pl";
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require "aeMB.pl";
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require "hdr_file_gen.pl";
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| Line 797... |
Line 798... |
return $hbox;
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return $hbox;
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}
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}
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sub get_all_hdl_files_list {
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sub get_all_files_list {
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my $soc=shift;
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my ($soc,$list_name)=@_;
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my @instances=$soc->soc_get_all_instances();
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my @instances=$soc->soc_get_all_instances();
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my $ip = ip->lib_new ();
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my $ip = ip->lib_new ();
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my @files;
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my @files;
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my $dir = Cwd::getcwd();
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my $dir = Cwd::getcwd();
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my $warnings;
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my $warnings;
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| Line 813... |
Line 814... |
my $module =$soc->soc_get_module($id);
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my $module =$soc->soc_get_module($id);
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my $module_name =$soc->soc_get_module_name($id);
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my $module_name =$soc->soc_get_module_name($id);
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my $category =$soc->soc_get_category($id);
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my $category =$soc->soc_get_category($id);
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my $inst =$soc->soc_get_instance_name($id);
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my $inst =$soc->soc_get_instance_name($id);
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my @new=$ip->ip_get_hdl_files( $category,$module);
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my @new=$ip->ip_get_files( $category,$module,$list_name);
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foreach my $f(@new){
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foreach my $f(@new){
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my $n="$project_dir$f";
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my $n="$project_dir$f";
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if (!(-f "$n") && !(-f "$f" )){
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if (!(-f "$n") && !(-f "$f" )){
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$warnings=(defined $warnings)? "$warnings WARNING: Can not find the hdl file \"$f\" which is required for \"$inst\" \n":"WARNING: Can not find the hdl file \"$f\" which is required for \"$inst\"\n ";
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$warnings=(defined $warnings)? "$warnings WARNING: Can not find \"$f\" which is required for \"$inst\" \n":"WARNING: Can not find \"$f\" which is required for \"$inst\"\n ";
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}
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}
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}
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}
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| Line 871... |
Line 872... |
mkpath("$target_dir/src_verilog/lib/",1,0755);
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mkpath("$target_dir/src_verilog/lib/",1,0755);
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mkpath("$target_dir/sw",1,0755);
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mkpath("$target_dir/sw",1,0755);
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#copy hdl codes in src_verilog
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#copy hdl codes in src_verilog
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my ($hdl_ref,$warnings)= get_all_hdl_files_list($soc);
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my ($file_ref,$warnings)= get_all_files_list($soc,"hdl_files");
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foreach my $f(@{$hdl_ref}){
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foreach my $f(@{$file_ref}){
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my $n="$project_dir$f";
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my $n="$project_dir$f";
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if (-f "$n") {
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if (-f "$n") {
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copy ("$n","$target_dir/src_verilog/lib");
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copy ("$n","$target_dir/src_verilog/lib");
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}elsif(-f "$f" ){
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}elsif(-f "$f" ){
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copy ("$f","$target_dir/src_verilog/lib");
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copy ("$f","$target_dir/src_verilog/lib");
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| Line 902... |
Line 903... |
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copy ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
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copy ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");
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# Write header file
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# Write header files
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my $file_h=aemb_generate_header($soc);
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my $file_h=generate_header_file($soc);
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open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!";
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open(FILE, ">lib/verilog/$name.h") || die "Can not open: $!";
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print FILE $file_h;
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print FILE $file_h;
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close(FILE) || die "Error closing file: $!";
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close(FILE) || die "Error closing file: $!";
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copy ("$dir/lib/verilog/$name.h","$target_dir/sw/");
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# Write Software files
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($file_ref,$warnings)= get_all_files_list($soc,"sw_files");
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foreach my $f(@{$file_ref}){
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my $name= basename($f);
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my $n="$project_dir$f";
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if (-f "$n") { #copy file
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copy ("$n","$target_dir/sw");
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}elsif(-f "$f" ){
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copy ("$f","$target_dir/sw");
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}elsif (-d "$n") {#copy folder
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dircopy ("$n","$target_dir/sw/$name");
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}elsif(-d "$f" ){
|
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dircopy ("$f","$target_dir/sw/$name");
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}
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}
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|
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copy ("$dir/lib/verilog/$name.h","$target_dir/sw/");
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|
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use File::Copy::Recursive qw(dircopy);
|
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dircopy("$dir/../src_processor/aeMB/compiler","$target_dir/sw/") or die("$!\n");
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|
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message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
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message_dialog("SoC \"$name\" has been created successfully at $target_dir/ " );
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exec($^X, $0, @ARGV);# reset ProNoC to apply changes
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}else {
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}else {
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message_dialog("Please define the SoC name!");
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message_dialog("Please define the SoC name!");
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}
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}
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