URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [perl/] [soc_gen.pl] - Diff between revs 17 and 18

Rev 17	Rev 18
Line 899...	Line 899...
`# $p`	`# $p`
`# );`	`# );`
`#}`	`#}`


`copy ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");`	`move ("$dir/lib/verilog/$name.v","$target_dir/src_verilog/");`



`# Write header files`	`# Write header files`
`my $file_h=generate_header_file($soc);`	`my $file_h=generate_header_file($soc);`
`open(FILE, ">lib/verilog/$name.h") \|\| die "Can not open: $!";`	`open(FILE, ">lib/verilog/$name.h") \|\| die "Can not open: $!";`
`print FILE $file_h;`	`print FILE $file_h;`
`close(FILE) \|\| die "Error closing file: $!";`	`close(FILE) \|\| die "Error closing file: $!";`
`copy ("$dir/lib/verilog/$name.h","$target_dir/sw/");`	`move ("$dir/lib/verilog/$name.h","$target_dir/sw/");`

`# Write Software files`	`# Write Software files`
`($file_ref,$warnings)= get_all_files_list($soc,"sw_files");`	`($file_ref,$warnings)= get_all_files_list($soc,"sw_files");`

`foreach my $f(@{$file_ref}){`	`foreach my $f(@{$file_ref}){`